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SPAK56F807VF80 PDF预览

SPAK56F807VF80

更新时间: 2024-11-13 15:52:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟外围集成电路
页数 文件大小 规格书
48页 853K
描述
16-BIT, 80MHz, OTHER DSP, PBGA160, MOLD ARRAY PROCESS, BGA-160

SPAK56F807VF80 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:160
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.57
地址总线宽度:16桶式移位器:YES
边界扫描:YES最大时钟频率:80 MHz
外部数据总线宽度:16格式:FIXED POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PBGA-B160
长度:15 mm低功率模式:YES
端子数量:160最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
座面最大高度:1.75 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
宽度:15 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

SPAK56F807VF80 数据手册

 浏览型号SPAK56F807VF80的Datasheet PDF文件第2页浏览型号SPAK56F807VF80的Datasheet PDF文件第3页浏览型号SPAK56F807VF80的Datasheet PDF文件第4页浏览型号SPAK56F807VF80的Datasheet PDF文件第5页浏览型号SPAK56F807VF80的Datasheet PDF文件第6页浏览型号SPAK56F807VF80的Datasheet PDF文件第7页 
DSP56F807/D  
Rev. 7.0, 1/2002  
DSP56F807  
Preliminary Technical Data  
DSP56F807 16-bit Digital Signal Processor  
Up to 40 MIPS at 80 MHz core frequency  
Up to 64K × 16- bit words each of external  
program and data memory  
DSP and MCU functionality in a unified,  
C-efficient architecture  
Two 6 channel PWM Modules  
Hardware DO and REP loops  
Four 4 channel, 12-bit ADCs  
MCU-friendly instruction set supports both  
DSP and controller functions: MAC, bit  
manipulation unit, 14 addressing modes  
Two Quadrature Decoders  
CAN 2.0 B Module  
Two Serial Communication Interfaces (SCIs)  
Serial Peripheral Interface (SPI)  
Up to four General Purpose Quad Timers  
JTAG/OnCETM port for debugging  
14 Dedicated and 18 Shared GPIO lines  
160-pin LQFP or 160 MAPBGA Packages  
60K × 16-bit words Program Flash  
2K × 16-bit words Program RAM  
8K × 16-bit words Data Flash  
4K × 16-bit words Data RAM  
2K × 16-bit words Boot Flash  
6
6
PWM Outputs  
PWMA  
PWMB  
RSTO  
EXTBOOT  
IRQB  
Current Sense Inputs  
Fault Inputs  
3
4
RESET  
IRQA  
VPP VCAPC  
2
V
V
V
V
SSA  
DD  
SS  
DDA  
6
PWM Outputs  
8
10*  
3
3
Current Sense Inputs  
Fault Inputs  
3
4
4
4
JTAG/  
OnCE  
Port  
Digital Reg  
Analog Reg  
A/D1  
A/D2  
ADCA  
Low Voltage  
Supervisor  
VREF  
A/D1  
A/D2  
ADCB  
4
4
VREF2  
Interrupt  
Controller  
Data ALU  
Address  
Generation  
Unit  
Bit  
Manipulation  
Unit  
Program Controller  
and  
Hardware Looping Unit  
Quadrature  
Decoder 0 /  
Quad Timer A  
16 x 16 + 36 36-Bit MAC  
Three 16-bit Input Registers  
Two 36-bit Accumulators  
4
Quadrature  
Decoder 1 /  
Quad Timer B  
Program Memory  
61440 x 16 Flash  
2048 x 16 SRAM  
PAB  
PLL  
CLKO  
4
2
PDB  
16-Bit  
DSP56800  
Core  
Quad Timer C  
XTAL  
Boot Flash  
2048 x 16 Flash  
Clock Gen  
Quad Timer D  
/ Alt Func  
EXTAL  
XDB2  
4
2
CGDB  
Data Memory  
8192 x 16 Flash  
4096 x 16 SRAM  
CAN 2.0A/B  
XAB1  
SCI0  
or  
GPIO  
XAB2  
INTERRUPT  
CONTROLS  
IPBB  
CONTROLS  
16  
2
2
A[00:05]  
SCI1  
or  
GPIO  
External  
Address Bus  
Switch  
16  
6
A[06:15] or  
GPIO-E2:E3 &  
GPIO-A0:A7  
COP/  
Watchdog  
COP RESET  
External  
Bus  
Interface  
Unit  
10  
16  
External  
Data Bus  
Switch  
MODULE CONTROLS  
Application-  
Specific  
Memory &  
Peripherals  
SPI  
or  
GPIO  
D[00:15]  
IPBus Bridge  
(IPBB)  
ADDRESS BUS [8:0]  
DATA BUS [15:0]  
PS Select  
DS Select  
WR Enable  
RD Enable  
4
Bus  
Control  
Dedicated  
GPIO  
14  
*includes TCS pin which is reserved for factory use and is tied to VSS  
Figure 1. DSP56F807 Block Diagram  
© Motorola, Inc., 2002. All rights reserved.  

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