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SPAK56F8345FG60 PDF预览

SPAK56F8345FG60

更新时间: 2024-11-13 21:21:55
品牌 Logo 应用领域
恩智浦 - NXP 时钟外围集成电路
页数 文件大小 规格书
148页 1420K
描述
0-BIT, 240MHz, OTHER DSP, PQFP128, 14 X 20 MM, 0.50 MM PITCH, 1.40 MM HEIGHT, PLASTIC, LQFP-128

SPAK56F8345FG60 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:128
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.59
地址总线宽度:桶式移位器:YES
边界扫描:YES最大时钟频率:240 MHz
外部数据总线宽度:格式:FIXED POINT
内部总线架构:MULTIPLEJESD-30 代码:R-PQFP-G128
长度:20 mm低功率模式:YES
端子数量:128封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

SPAK56F8345FG60 数据手册

 浏览型号SPAK56F8345FG60的Datasheet PDF文件第2页浏览型号SPAK56F8345FG60的Datasheet PDF文件第3页浏览型号SPAK56F8345FG60的Datasheet PDF文件第4页浏览型号SPAK56F8345FG60的Datasheet PDF文件第5页浏览型号SPAK56F8345FG60的Datasheet PDF文件第6页浏览型号SPAK56F8345FG60的Datasheet PDF文件第7页 
Freescale Semiconductor, Inc.  
MC56F8345/D  
Rev. 8.0, 6/2004  
56F8345  
Preliminary Technical Data  
56F8345 16-bit Hybrid Controller  
• Up to 60 MIPS at 60MHz core frequency  
• Two Quadrature Decoders  
• DSP and MCU functionality in a unified,  
C-efficient architecture  
• FlexCAN module  
• Optional On-Chip Regulator  
• 128KB Program Flash  
• 4KB Program RAM  
• 8KB Data Flash  
• Two Serial Communication Interfaces (SCIs)  
• Up to two Serial Peripheral Interface (SPIs)  
• Up to four general-purpose Quad Timers  
• Computer Operating Properly (COP)/Watchdog  
• 8KB Data RAM  
• 8KB Boot Flash  
• JTAG/Enhanced On-Chip Emulation (OnCE™) for  
unobtrusive, real-time debugging  
• Two 6-channel PWM modules  
• Four 4-channel, 12-bit ADCs  
• Temperature Sensor  
• Up to 49 GPIO lines  
• 128-pin LQFP Package  
OCR_DIS  
RSTO  
V
V
V
V
V
V
SSA  
PP  
CAP  
DD  
SS  
DDA  
5
RESET  
2
4
7
5
2
6
JTAG/  
EOnCE  
Port  
PWM Outputs  
PWMA  
Digital Reg  
Analog Reg  
Current Sense Inputs  
3
Low Voltage  
Supervisor  
16-Bit  
56800E Core  
or GPIOC  
4
Fault Inputs  
Data ALU  
Program Controller  
and Hardware  
Looping Unit  
Address  
Generation Unit  
Bit  
Manipulation  
Unit  
16 x 16 + 36 -->36-Bit MAC  
Three 16-bit Input Registers  
Four 36-bit Accumulators  
6
PWM Outputs  
PWMB  
3
Current Sense Inputs  
or GPIOD  
PAB  
PDB  
CDBR  
CDBW  
4
4
Fault Inputs  
AD0  
ADCA  
AD1  
4
5
4
Memory  
R/W Control  
XDB2  
XAB1  
XAB2  
VREF  
6
Program Memory  
64K x 16 Flash  
2K x 16 RAM  
4K x 16 Boot  
Flash  
* External  
Address Bus  
Switch  
A8-13 or GPIOA0-5  
GPIOB0-4 or A16-20  
AD0  
5
ADCB  
PAB  
4
AD1  
System Bus  
Control  
PDB  
CDBR  
CDBW  
TEMP_SENSE  
* External  
Data  
Bus Switch  
4
Data Memory  
4K x 16 Flash  
4K x 16 RAM  
D7-10 or GPIOF0-3  
GPIOD0-5 or CS2-7  
Quadrature  
Decoder 0 or  
Quad  
4
Timer A or  
GPIOC  
* Bus  
Control  
6
Quadrature  
Decoder 1 or  
Quad  
Timer B or  
SP1I or  
IPBus Bridge (IPBB)  
4
Peripheral  
Device Selects  
RW  
IPAB IPWDB  
IPRDB  
Control  
GPIOC  
Decoding  
* EMI not functional in  
this package; use as  
GPIO pins  
Quad Timer  
C or GPIOE  
Peripherals  
2
Clock  
resets  
PLL  
Quad Timer  
D or GPIOE  
4
2
P
System  
Integration  
SPI0 or  
GPIOE  
SCI1 or  
GPIOD  
SCI0 or  
COP/  
Interrupt  
O
R
O
S
C
Clock  
Generator  
XTAL  
FlexCAN  
GPIOE Watchdog Controller  
EXTAL  
Module  
2
4
2
CLKO  
IRQA IRQB  
CLKMODE  
56F8345 Block Diagram - 128 LQFP  
© Motorola, Inc., 2004. All rights reserved.  
For More Information On This Product,  
Go to: www.freescale.com  

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