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SPAK56F8357PY60

更新时间： 2024-09-25 19:57:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
156页 2252K
描述
16-BIT, 240MHz, OTHER DSP, PQFP160, 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-160

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SPAK56F8357PY60 数据手册

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MC56F8357/D  
Rev. 1.0, 10/2003  
56F8357  
Preliminary Technical Data  
56F8357 16-bit Digital Signal Processor  
• Up to 60 MIPS at 60MHz core frequency  
• Temperature Sensor  
• DSP and MCU functionality in a unified,  
C-efficient architecture  
• Two Quadrature Decoders  
• Optional on-chip regulator  
• FlexCAN Module  
• Access up to 4MB of off-chip program and 32MB  
of data memory  
• Two Serial Communication Interfaces (SCIs)  
• Up to two Serial Peripheral Interfaces (SPIs)  
• Up to four General Purpose Quad Timers  
• Computer Operating Properly (COP) / Watchdog  
• Chip Select Logic for glueless interface to ROM  
and SRAM  
• 256KB of Program Flash  
• 4KB of Program RAM  
• 8KB of Data Flash  
• JTAG/Enhanced On-Chip Emulation (OnCE™) for  
unobtrusive, real-time debugging  
• 16KB of Data RAM  
• Up to 76 GPIO lines  
• 16KB Boot Flash  
• 160-pin LQFP Package  
• Two 6-channel PWM Modules  
• Four 4-channel, 12-bit ADCs  
OCR_DIS  
RSTO  
EMI_MODE  
EXTBOOT  
* Configuration  
shown for on-chip  
2.5V regulator  
V
2
V
*
V
V
V
2
V
SSA  
PP  
CAP  
DD  
SS  
DDA  
5
RESET  
4
7
6
6
6
JTAG/  
EOnCE  
Port  
PWM Outputs  
Digital Reg  
Low Voltage  
Supervisor  
Analog Reg  
PWMA  
3
4
16-Bit  
56800E Core  
Current Sense Inputs/GPIOC  
Fault Inputs  
Data ALU  
Bit  
Manipulation  
Unit  
Program Controller  
and  
Hardware Looping Unit  
Address  
Generation Unit  
PWM Outputs  
PWMB  
16 x 16 + 36 Æ 36-Bit MAC  
Three 16-bit Input Registers  
Four 36-bit Accumulators  
3
4
Current Sense Inputs/GPIOD  
Fault Inputs  
PAB  
4
4
PDB  
CDBR  
CDBW  
A/D0  
ADCA  
A/D1  
5
4
4
R/W Control  
6
VREF  
Memory  
A0-5 or GPIOA8-13  
XDB2  
XAB1  
XAB2  
PAB  
2
8
4
A6-7 or GPIOE2-3  
A8-15 or GPIOA0-7  
A/D0  
A/D1  
External  
Address Bus  
Switch  
Program Memory  
128K x 16 Flash  
2K x 16 RAM  
8K x 16 Boot  
Flash  
ADCB  
GPIOB0-3 (A16-19)  
GPIOB4 (A20,  
prescaler_clock)  
Temp_Sense  
1
3
System Bus  
Control  
PDB  
CDBR  
CDBW  
Quadrature  
Decoder 0/  
Quad  
Timer A/  
GPIOC  
GPIOB5-7 (A21-23,  
clk0-3**)  
Data Memory  
4K x 16 Flash  
8K x 16 RAM  
4
7
8
D0-6 or GPIOF9-15  
D7-15 or GPIOF0-8  
External Data  
Bus Switch  
Quadrature  
Decoder 1/  
Quad  
Timer B/  
SPI1/GPIOC  
IPBus Bridge (IPBB)  
WR  
RD  
4
2
Peripheral  
Device Selects  
Bus Control  
6
RW  
Control  
IPAB  
IPWDB  
IPRDB  
GPIOD0-5 or CS2-7  
PS (CS0) or GPIOD8  
DS (CS1) or GPIOD9  
Quad  
Timer C/  
GPIOE  
Decoding  
Peripherals  
**See Table 2-2  
for explanation  
Quad  
Timer D/  
GPIOE  
Clock resets  
P
4
2
PLL  
System  
Integration  
Module  
FlexCAN  
O
R
SCI1 or  
GPIOD  
COP/  
Watchdog  
SPI0 or  
GPIOE  
O
S
C
SCI0 or  
GPIOE  
Interrupt  
Controller  
Clock  
Generator  
XTAL  
EXTAL  
4
2
2
IRQA  
IRQB  
CLKO  
CLKMODE  
56F8357 Block Diagram  
© Motorola, Inc., 2003. All rights reserved.  
1234567...156

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