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SPAK56F826BU80 PDF预览

SPAK56F826BU80

更新时间: 2024-11-13 15:52:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟外围集成电路
页数 文件大小 规格书
53页 829K
描述
16-BIT, 80MHz, OTHER DSP, PQFP100, LQFP-100

SPAK56F826BU80 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.59
Is Samacsys:N其他特性:ALSO REQUIRES 3.3V SUPPLY
地址总线宽度:16桶式移位器:YES
边界扫描:YES最大时钟频率:80 MHz
外部数据总线宽度:16格式:FIXED POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PQFP-G100
长度:14 mm低功率模式:YES
端子数量:100最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压:2.75 V
最小供电电压:2.25 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
宽度:14 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

SPAK56F826BU80 数据手册

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DSP56F826/D  
Rev. 4.0, 1/2002  
DSP56F826  
Preliminary Technical Data  
DSP56F826 16-bit Digital Signal Processor  
Up to 40 MIPS at 80MHz core frequency  
Up to 64K × 16-bit words each of external  
memory expansion for Program and Data  
memory  
DSP and MCU functionality in a unified,  
C-efficient architecture  
One Serial Port Interface (SPI)  
Hardware DO and REP loops  
One additional SPI or two optional Serial  
Communication Interfaces (SCI)  
MCU-friendly instruction set supports both  
DSP and controller functions: MAC, bit  
manipulation unit, 14 addressing modes  
One Synchronous Serial Interface (SSI)  
One General Purpose Quad Timer  
JTAG/OnCEfor debugging  
100-pin LQFP Package  
31.5K × 16-bit words Program Flash  
512 × 16-bit words Program RAM  
2K × 16-bit words Data Flash  
4K × 16-bit words Data RAM  
2K × 16-bit words BootFLASH  
16 dedicated and 30 shared GPIO  
One Time-of-Day module  
EXTBOOT  
IRQB  
RESET  
IRQA  
V
V
SSIO  
V
V
SS  
V
V
SSA  
DDIO  
DD  
DDA  
6
3
4
4
4
Low Voltage Supervisor  
JTAG/  
OnCE  
Port  
Analog Reg  
TOD  
Timer  
Data ALU  
16 x 16 + 36 36-Bit MAC  
Three 16-bit Input Registers  
Two 36-bit Accumulators  
Address  
Generation  
Unit  
Bit  
Program Controller  
and  
Hardware Looping Unit  
Interrupt  
Controller  
Manipulation  
Unit  
Program Memory  
32252 x 16 Flash  
512 x 16 SRAM  
PAB  
PDB  
Quad Timer  
or  
GPIO  
CLKO  
PLL  
16-Bit  
DSP56800  
Core  
4
XTAL  
Boot Flash  
2048 x 16 Flash  
Clock Gen  
EXTAL  
XDB2  
CGDB  
XAB1  
XAB2  
Data Memory  
2048 x 16 Flash  
4096 x 16 SRAM  
SSI  
or  
GPIO  
6
INTERRUPT  
CONTROLS  
IPBB  
CONTROLS  
16  
SCI0 & SCI1  
External  
Address Bus  
Switch  
16  
A[00:15]  
or  
GPIO  
COP  
or  
SPI0  
RESET  
COP/  
Watchdog  
4
4
16  
16  
External  
Data Bus  
Switch  
SPI1  
or  
GPIO  
External  
Bus  
Interface  
Unit  
MODULE CONTROLS  
D[00:15]  
Application-  
Specific  
Memory &  
Peripherals  
IPBus Bridge  
(IPBB)  
ADDRESS BUS [8:0]  
DATA BUS [15:0]  
PS Select[0]  
DS Select[1]  
WR Enable  
RD Enable  
Bus  
Control  
Dedicated  
GPIO  
16  
Figure 1. DSP56F826 Block Diagram  
© Motorola, Inc., 2002. All rights reserved.  

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