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SPAK56854FG120 PDF预览

SPAK56854FG120

更新时间: 2024-11-13 20:45:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 时钟外围集成电路
页数 文件大小 规格书
52页 2114K
描述
Digital Signal Processor, 16-Ext Bit, 4MHz, CMOS, PQFP128, LQFP-128

SPAK56854FG120 技术参数

生命周期:Transferred零件包装代码:QFP
包装说明:LFQFP,针数:128
Reach Compliance Code:unknown风险等级:5.62
其他特性:ALSO REQUIRES 3.3V SUPPLY地址总线宽度:21
桶式移位器:YES边界扫描:YES
最大时钟频率:4 MHz外部数据总线宽度:16
格式:FIXED POINT内部总线架构:MULTIPLE
JESD-30 代码:R-PQFP-G128长度:20 mm
低功率模式:YES端子数量:128
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装形状:RECTANGULAR封装形式:FLATPACK, LOW PROFILE, FINE PITCH
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压:1.98 V最小供电电压:1.62 V
标称供电电压:1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

SPAK56854FG120 数据手册

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DSP56854/D  
Rev. 3.0 8/2003  
DSP56854  
Preliminary Technical Data  
DSP56854 16-bit Digital Signal Processor  
• 120 MIPS at 120MHz  
• Serial Port Interface (SPI)  
• 16K x 16-bit Program SRAM  
• 16K x 16-bit Data SRAM  
• 1K x 16-bit Boot ROM  
• 8-bit Parallel Host Interface  
• General Purpose 16-bit Quad Timer  
• JTAG/Enhanced On-Chip Emulation (OnCE™) for  
unobtrusive, real-time debugging  
• Access up to 2M words of program or 8M data  
memory  
• Computer Operating Properly (COP)/Watchdog  
Timer  
• Chip Select Logic for glue-less interface to ROM  
and SRAM  
• Time-of-Day (TOD)  
• 128 LQFP package  
• Up to 41 GPIO  
• Six (6) independent channels of DMA  
• Enhanced Synchronous Serial Interfaces (ESSI)  
• Two (2) Serial Communication Interfaces (SCI)  
V
V
6
V
V
SSA  
V
V
SSIO  
SS  
DDA  
DDIO  
DD  
6
10  
11  
6
JTAG/  
Enhanced  
OnCE  
16-Bit  
DSP56800E Core  
Program Controller  
and  
Hardware Looping Unit  
Address  
Generation Unit  
Data ALU  
16 x 16 + 36 36-Bit MAC  
Three 16-bit Input Registers  
Four 36-bit Accumulators  
Bit  
Manipulation  
Unit  
PAB  
PDB  
CDBR  
CDBW  
Memory  
XDB2  
Program Memory  
XAB1  
16,384 x 16 SRAM  
XAB2  
System  
Bus  
Control  
DMA  
6 channel  
Boot ROM  
PAB  
1024 x 16 ROM  
PDB  
Data Memory  
16,384 x 16 SRAM  
CDBR  
CDBW  
IPBus Bridge (IPBB)  
Decoding  
Peripherals  
POR  
CLKO  
IPBus CLK  
3
MODEA-C or  
(GPIOH0-H2)  
System  
Integration  
Module  
COP/TOD CLK  
RSTO  
External Address  
Bus Switch  
A0-20 [20:0]  
RESET  
External Data  
Bus Switch  
External Bus  
Interface Unit  
D0-D15 [15:0]  
EXTAL  
XTAL  
Clock  
Generator  
ESSI0  
or  
GPIOC  
2 SCI  
or  
GPIOE  
Quad  
Timer  
or  
SPI  
or  
GPIOF  
Host  
Interrupt  
COP/  
Watch-  
dog  
Time  
of  
Day  
RD Enable  
WR Enable  
Interface Controller  
or  
GPIOB  
Bus Control  
OSC PLL  
GPIOG  
CS0-CS3[3:0] or  
GPIOA0-GPIOA3[3:0]  
6
4
4
4
16  
IRQA  
IRQB  
Figure 1. DSP56854 Block Diagram  
© Motorola, Inc., 2003. All rights reserved.  

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