SNJ54ACT574FK

更新时间： 2024-09-09 05:04:39

品牌	Logo	应用领域
德州仪器 - TI		触发器输出元件
页数	文件大小	规格书
15页	526K
描述
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

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SNJ54ACT574FK 数据手册

SN54ACT574, SN74ACT574

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCAS537D – OCTOBER 1995 – REVISED NOVEMBER 2002

SN54ACT574 . . . J OR W PACKAGE

SN74ACT574 . . . DB, DW, N, NS, OR PW PACKAGE

(TOP VIEW)

4.5-V to 5.5-V V

Operation

Inputs Accept Voltages to 5.5 V

Max t of 9 ns at 5 V

Inputs Are TTL-Voltage Compatible

CLK

description/ordering information

These 8-bit flip-flops feature 3-state outputs

designed specifically for driving highly capacitive

or relatively low-impedance loads. The devices

are particularly suitable for implementing buffer

registers, I/O ports, bidirectional bus drivers, and

working registers.

GND

The eight flip-flops of the ’ACT574 devices are

D-type edge-triggered flip-flops. On the positive

transition of the clock (CLK) input, the Q outputs

are set to the logic levels set up at the data (D)

inputs.

SN54ACT574 . . . FK PACKAGE

(TOP VIEW)

A buffered output-enable (OE) input can be used

to place the eight outputs in either a normal logic

state (high or low logic levels) or the

high-impedance state. In the high-impedance

state, the outputs neither load nor drive the bus

lines significantly. The high-impedance state and

the increased drive provide the capability to drive

bus lines in a bus-organized system without need

for interface or pullup components.

20 19

9 10 11 12 13

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

PDIP – N

Tube

SN74ACT574N

Tube

SN74ACT574DW

SN74ACT574DWR

SN74ACT574NSR

SN74ACT574DBR

SN74ACT574PWR

SNJ54ACT574J

SOIC – DW

ACT574

Tape and reel

Tube

–40°C to 85°C

SOP – NS

SSOP – DB

TSSOP – PW

CDIP – J

ACT574

AD574

SNJ54ACT574J

SNJ54ACT574W

SNJ54ACT574FK

–55°C to 125°C

CFP – W

Tube

SNJ54ACT574W

SNJ54ACT574FK

LCCC – FK

Tube

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...15

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与SNJ54ACT574FK相关器件

型号	品牌	获取价格	描述	数据表
SNJ54ACT574J	TI	获取价格	OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54ACT574W	TI	获取价格	OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SNJ54ACT74FK	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SNJ54ACT74J	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SNJ54ACT74W	TI	获取价格	DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SNJ54ACT86FK	TI	获取价格	QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SNJ54ACT86J	TI	获取价格	QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SNJ54ACT86W	TI	获取价格	QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
SNJ54ACT8990GB	TI	获取价格	TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES
SNJ54ACT8990HV	TI	获取价格	TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES

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