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SNJ54ACT8990HV

更新时间： 2024-09-08 22:42:55

品牌	Logo	应用领域
德州仪器 - TI		总线控制器微控制器和处理器外围集成电路 uCs集成电路 uPs集成电路
页数	文件大小	规格书
15页	303K
描述
TEST-BUS CONTROLLERS IEEE STD 1149.1 JTAG TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES

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SNJ54ACT8990HV 技术参数

生命周期：	Active	零件包装代码：	QFP
包装说明：	QFP-68	针数：	68
Reach Compliance Code：	not_compliant	HTS代码：	8542.31.00.01
Factory Lead Time：	35 weeks	风险等级：	5.05
Is Samacsys：	N	外部数据总线宽度：	16
JESD-30 代码：	S-GQFP-F68	长度：	12.51 mm
端子数量：	68	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	QFF	封装等效代码：	QFL68,.5SQ,25
封装形状：	SQUARE	封装形式：	FLATPACK
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	5 V
认证状态：	Not Qualified	筛选级别：	MIL-PRF-38535
座面最大高度：	3.86 mm	子类别：	Other Microprocessor ICs
最大压摆率：	0.45 mA	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子形式：	FLAT
端子节距：	0.635 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	12.51 mm
uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT	Base Number Matches：	1

SNJ54ACT8990HV 数据手册

SN54ACT8990, SN74ACT8990

TEST-BUS CONTROLLERS

IEEE STD 1149.1 (JTAG) TAP MASTERS WITH 16-BIT GENERIC HOST INTERFACES

SCAS190E – JUNE 1990 – REVISED JANUARY 1997

Members of the Texas Instruments

SCOPE Family of Testability Products

Execute Instructions for Up to 2 Clock

Cycles

Compatible With the IEEE Standard

1149.1-1990 (JTAG) Test Access Port and

Boundary-Scan Architecture

Each Device Includes Four Bidirectional

Event Pins for Additional Test Capability

Inputs Are TTL-Voltage Compatible

Control Operation of Up to Six Parallel

Target Scan Paths

EPIC (Enhanced-Performance Implanted

CMOS) 1-µm Process

Accommodate Pipeline Delay to Target of

Up to 31 Clock Cycles

Packaged in 44-Pin Plastic Leaded Chip

Carrier (FN), 68-Pin Ceramic Pin Grid Array

(GB), and 68-Pin Ceramic Quad Flat

Packages (HV)

Scan Data Up to 2 Clock Cycles

description

The ’ACT8990 test-bus controllers (TBC) are members of the Texas Instruments SCOPE testability

integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary

scan to facilitate testing of complex circuit-board assemblies. The ’ACT8990 differ from other SCOPE

integrated circuits. Their function is to control the JTAG serial-test bus rather than being target

boundary-scannable devices.

TherequiredsignalsoftheJTAGserial-testbus–testclock(TCK), testmodeselect(TMS), testdatainput(TDI),

and test data output (TDO) can be connected from the TBC to a target device without additional logic. This is

done as a chain of IEEE Standard 1149.1-1990 boundary-scannable components that share the same

serial-testbus. TheTBCgeneratesTMSandTDIsignalsforitstarget(s), receivesTDOsignalsfromitstarget(s),

and buffers its test clock input (TCKI) to a test clock output (TCKO) for distribution to its target(s). The TMS, TDI,

and TDO signals can be connected to a target directly or via a pipeline, with a retiming delay of up to 31 bits.

Since the TBC can be configured to generate up to six separate TMS signals [TMS (5 –0)], it can be used to

control up to six target scan paths that are connected in parallel (i.e., sharing common TCK, TDI, and TDO

signals).

While most operations of the TBC are synchronous to TCKI, a test-off (TOFF) input is provided for output control

of the target interface, and a test-reset (TRST) input is provided for hardware/software reset of the TBC. In

addition, four event [EVENT (3–0)] I/Os are provided for asynchronous communication to target device(s).

Each event has its own event generation/detection logic, and detected events can be counted by two 16-bit

counters.

The TBC operates under the control of a host microprocessor/microcontroller via the 5-bit address bus

[ADRS (4–0)] and the 16-bit read/write data bus [DATA (15–0)]. Read (RD) and write (WR) strobes are

implemented such that the critical host-interface timing is independent of the TCKI period. Any one of

24 registers can be addressed for read and/or write operations. In addition to control and status registers, the

TBC contains two command registers, a read buffer, and a write buffer. Status of the TBC is transmitted to the

host via ready (RDY) and interrupt (INT) outputs.

Major commands can be issued by the host to cause the TBC to generate the TMS sequences necessary to

move the target(s) from any stable test-access-port (TAP) controller state to any other stable TAP state, to

execute instructions in the Run-Test/Idle TAP state, or to scan instruction or test data through the target(s). A

32-bit counter can be preset to allow a predetermined number of execution or scan operations.

Serial data that appears at the selected TDI input (TDI1 or TDI0) is transferred into the read buffer, which can

be read by the host to obtain up to 16 bits of the serial-data stream. Serial data that is transmitted from the TDO

output is written by the host to the write buffer.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and EPIC are trademarks of Texas Instruments Incorporated.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...15

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与SNJ54ACT8990HV相关器件

型号	品牌	获取价格	描述	数据表
SNJ54ACT8997FK	TI	获取价格	SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 JTAG TAP
SNJ54ACT8997JT	TI	获取价格	SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTROLLED IEEE STD 1149.1 JTAG TAP
SNJ54AHC00FK	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SNJ54AHC00J	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SNJ54AHC00W	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SNJ54AHC02FK	TI	获取价格	QUADRUPLE 2 - INPUT POSITIVE - NOR GATES
SNJ54AHC02J	TI	获取价格	QUADRUPLE 2 - INPUT POSITIVE - NOR GATES
SNJ54AHC02W	TI	获取价格	QUADRUPLE 2 - INPUT POSITIVE - NOR GATES
SNJ54AHC02WR	TI	获取价格	AHC/VHC/H/U/V SERIES, QUAD 2-INPUT NOR GATE, CDFP14, CERAMIC, DFP-14
SNJ54AHC04FK	TI	获取价格	HEX INVERTERS

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