5秒后页面跳转
捷配首页

Datasheet > SNJ54AHC125J
SNJ54AHC125J PDF预览

SNJ54AHC125J

更新时间： 2024-01-11 18:04:42
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
19页 647K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SNJ54AHC125J 技术参数

生命周期：Active零件包装代码：DIP
包装说明：DIP, DIP14,.3针数：14
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.24
控制类型：ENABLE LOW计数方向：UNIDIRECTIONAL
系列：AHC/VHC/H/U/VJESD-30 代码：R-GDIP-T14
长度：19.56 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.05 A
位数：1功能数量：4
端口数量：2端子数量：14
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DIP
封装等效代码：DIP14,.3封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：2/5.5 V
最大电源电流（ICC）：0.04 mAProp。Delay @ Nom-Sup：8.5 ns
传播延迟（tpd）：13 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535座面最大高度：5.08 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：3.3 V
表面贴装：NO技术：CMOS
温度等级：MILITARY端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.67 mm
Base Number Matches：1

SNJ54AHC125J 数据手册

 浏览型号SNJ54AHC125J的Datasheet PDF文件第2页浏览型号SNJ54AHC125J的Datasheet PDF文件第3页浏览型号SNJ54AHC125J的Datasheet PDF文件第4页浏览型号SNJ54AHC125J的Datasheet PDF文件第5页浏览型号SNJ54AHC125J的Datasheet PDF文件第6页浏览型号SNJ54AHC125J的Datasheet PDF文件第7页 
SN54AHC125, SN74AHC125  
QUADRUPLE BUS BUFFER GATES  
WITH 3-STATE OUTPUTS  
SCLS256J – DECEMBER 1995 – REVISED JULY 2003  
Operating Range 2-V to 5.5-V V  
CC  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
SN54AHC125 . . . J OR W PACKAGE  
SN74AHC125 . . . D, DB, DGV, N, NS,  
OR PW PACKAGE  
SN74AHC125 . . . RGY PACKAGE  
(TOP VIEW)  
SN54AHC125 . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
14  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
3
2
1
20 19  
18 4A  
1A  
1Y  
13 4OE  
12 4A  
2
3
4
5
6
1Y  
NC  
4
5
6
7
8
17  
16  
15  
14  
NC  
4Y  
4A  
4Y  
3OE  
3A  
3Y  
11  
10  
9
2OE  
2A  
4Y  
2OE  
NC  
3OE  
3A  
NC  
3OE  
2Y  
2A  
9 10 11 12 13  
7
8
8
GND  
NC – No internal connection  
description/ordering information  
The ’AHC125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.  
Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective  
gate passes the data from the A input to its Y output.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
QFN – RGY  
PDIP – N  
Tape and reel  
Tube  
SN74AHC125RGYR  
SN74AHC125N  
HA125  
SN74AHC125N  
Tube  
SN74AHC125D  
SOIC – D  
AHC125  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74AHC125DR  
SN74AHC125NSR  
SN74AHC125DBR  
SN74AHC125PW  
SN74AHC125PWR  
SN74AHC125DGVR  
SNJ54AHC125J  
–40°C to 85°C  
SOP – NS  
AHC125  
HA125  
SSOP – DB  
TSSOP – PW  
HA125  
Tape and reel  
Tape and reel  
Tube  
TVSOP – DGV  
CDIP – J  
HA125  
SNJ54AHC125J  
SNJ54AHC125W  
SNJ54AHC125FK  
–55°C to 125°C  
CFP – W  
Tube  
SNJ54AHC125W  
SNJ54AHC125FK  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...19

中文翻译

下载PDF

SNJ54AHC125J 替代型号

型号 品牌 替代类型 描述 数据表
5962-9686801QCA TI

完全替代

 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74AHC125NE4 TI

类似代替

 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74AHC125N TI

类似代替

 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

与SNJ54AHC125J相关器件

型号 品牌 获取价格 描述 数据表
SNJ54AHC125W TI

获取价格

 		QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SNJ54AHC126FK TI

获取价格

 		QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SNJ54AHC126FKR TI

获取价格

 		AHC/VHC/H/U/V SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20
SNJ54AHC126J TI

获取价格

 		QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SNJ54AHC126W TI

获取价格

 		QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SNJ54AHC126WR TI

获取价格

 		AHC/VHC/H/U/V SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CDFP14, CERAMIC, DFP-14
SNJ54AHC132FK TI

获取价格

 		QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
SNJ54AHC132J TI

获取价格

 		QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
SNJ54AHC132W TI

获取价格

 		QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
SNJ54AHC132WR TI

获取价格

 		AHC/VHC/H/U/V SERIES, QUAD 2-INPUT NAND GATE, CDFP14, CERAMIC, DFP-14

与SNJ54AHC125J相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证