5秒后页面跳转
SNJ54AHC125FKR PDF预览

SNJ54AHC125FKR

更新时间: 2024-11-04 21:18:59
品牌 Logo 应用领域
德州仪器 - TI 驱动输出元件逻辑集成电路
页数 文件大小 规格书
27页 1396K
描述
AHC/VHC/H/U/V SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20

SNJ54AHC125FKR 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCN,针数:20
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.56系列:AHC/VHC/H/U/V
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
位数:1功能数量:4
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
传播延迟(tpd):13 ns认证状态:Not Qualified
筛选级别:MIL-PRF-38535座面最大高度:2.03 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD宽度:8.89 mm
Base Number Matches:1

SNJ54AHC125FKR 数据手册

 浏览型号SNJ54AHC125FKR的Datasheet PDF文件第2页浏览型号SNJ54AHC125FKR的Datasheet PDF文件第3页浏览型号SNJ54AHC125FKR的Datasheet PDF文件第4页浏览型号SNJ54AHC125FKR的Datasheet PDF文件第5页浏览型号SNJ54AHC125FKR的Datasheet PDF文件第6页浏览型号SNJ54AHC125FKR的Datasheet PDF文件第7页 
SN54AHC125  
SN74AHC125  
www.ti.com  
SCLS256K DECEMBER 1995REVISED JUNE 2013  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
Check for Samples: SN54AHC125, SN74AHC125  
1
FEATURES  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Operating Range 2-V to 5.5-V  
SN54AHC125 . . . J OR W PACKAGE  
SN74AHC125 . . . D, DB, DGV, N, NS,  
OR PW PACKAGE  
SN74AHC125 . . . RGY PACKAGE  
(TOP VIEW)  
SN54AHC125 . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
14  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
VCC  
4OE  
4A  
3
2
1
20 19  
18 4A  
1A  
1Y  
13 4OE  
12 4A  
2
3
4
5
6
1Y  
NC  
4
5
6
7
8
17  
16  
15  
14  
NC  
4Y  
1Y  
11  
10  
9
2OE  
2A  
4Y  
2OE  
NC  
2OE  
2A  
4Y  
3OE  
3A  
NC  
3OE  
3OE  
3A  
2Y  
2Y  
2A  
9 10 11 12 13  
7
8
8
GND  
3Y  
NC − No internal connection  
DESCRIPTION  
The ’AHC125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs.  
Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective  
gate passes the data from the A input to its Y output.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
FUNCTION TABLE  
(EACH BUFFER)  
INPUTS  
OUTPUT  
OE  
L
A
H
L
Y
H
L
L
H
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)  
1
2
10  
1OE  
1A  
3OE  
3
9
8
1Y  
3A  
3Y  
4
5
13  
12  
2OE  
2A  
4OE  
4A  
6
11  
2Y  
4Y  
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 1995–2013, Texas Instruments Incorporated  
 

与SNJ54AHC125FKR相关器件

型号 品牌 获取价格 描述 数据表
SNJ54AHC125J TI

获取价格

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SNJ54AHC125W TI

获取价格

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SNJ54AHC126FK TI

获取价格

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SNJ54AHC126FKR TI

获取价格

AHC/VHC/H/U/V SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20
SNJ54AHC126J TI

获取价格

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SNJ54AHC126W TI

获取价格

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SNJ54AHC126WR TI

获取价格

AHC/VHC/H/U/V SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, CDFP14, CERAMIC, DFP-14
SNJ54AHC132FK TI

获取价格

QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
SNJ54AHC132J TI

获取价格

QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS
SNJ54AHC132W TI

获取价格

QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS