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SN74LVC74APW PDF预览

SN74LVC74APW

更新时间： 2024-11-17 22:16:19
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管PC
页数 文件大小 规格书
9页 132K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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中文翻译

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SN74LVC74APW 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP14,.25针数：14
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.67Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：304436
Samacsys Pin Count：14Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Small Outline PackagesSamacsys Footprint Name：pw(r-pdso-g14)
Samacsys Released Date：2017-01-12 12:59:53Is Samacsys：N
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G14
JESD-609代码：e4长度：5 mm
负载电容（CL）：50 pF逻辑集成电路类型：D FLIP-FLOP
最大频率@ Nom-Sup：150000000 Hz最大I（ol）：0.024 A
湿度敏感等级：1位数：1
功能数量：2端子数量：14
最高工作温度：125 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TUBE峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：5.2 ns传播延迟（tpd）：7.1 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：4.4 mm
最小 fmax：150 MHzBase Number Matches：1

SN74LVC74APW 数据手册

 浏览型号SN74LVC74APW的Datasheet PDF文件第2页浏览型号SN74LVC74APW的Datasheet PDF文件第3页浏览型号SN74LVC74APW的Datasheet PDF文件第4页浏览型号SN74LVC74APW的Datasheet PDF文件第5页浏览型号SN74LVC74APW的Datasheet PDF文件第6页浏览型号SN74LVC74APW的Datasheet PDF文件第7页 
SN54LVC74A, SN74LVC74A  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH CLEAR AND PRESET  
SCAS287H – JANUARY 1993 – REVISED JUNE 1998  
SN54LVC74A . . . J OR W PACKAGE  
SN74LVC74A . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1CLR  
1D  
V
CC  
2CLR  
2D  
1
2
3
4
5
6
7
14  
13  
12  
11  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
1CLK  
1PRE  
1Q  
2CLK  
10 2PRE  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
9
8
1Q  
2Q  
2Q  
CC  
A
GND  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Inputs Accept Voltages to 5.5 V  
SN54LVC74A . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, and Ceramic Flat (W) Packages,  
Ceramic Chip Carriers (FK), and DIPs (J)  
3
2
1
20 19  
18  
1CLK  
NC  
2D  
4
5
6
7
8
17  
16  
15  
14  
NC  
description  
1PRE  
NC  
2CLK  
NC  
The SN54LVC74A dual positive-edge-triggered  
D-type flip-flop is designed for 2.7-V to 3.6-V V  
1Q  
2PRE  
CC  
9 10 11 12 13  
operation and the SN74LVC74A dual positive-  
edge-triggered D-type flip-flop is designed for  
1.65-V to 3.6-V V  
operation.  
CC  
NC – No internal connection  
A low level at the preset (PRE) or clear (CLR)  
inputs sets or resets the outputs, regardless of the  
levels of the other inputs. When PRE and CLR are  
inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on  
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related  
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without  
affecting the levels at the outputs.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
The SN54LVC74A is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LVC74A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

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SN74LVC74APW 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC74APWT TI

完全替代

 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74LVC74APWLE TI

完全替代

 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74LVC74APWR TI

类似代替

 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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