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SN74LVC74A-Q1 PDF预览

SN74LVC74A-Q1

更新时间： 2024-10-01 11:58:39
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
11页 222K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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SN74LVC74A-Q1 数据手册

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SN74LVC74A-Q1  
www.ti.com ...................................................................................................................................................... SCES481C–AUGUST 2003–REVISED APRIL 2008  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH CLEAR AND PRESET  
1
FEATURES  
•
Qualified for Automotive Applications  
D OR PW PACKAGE  
(TOP VIEW)  
•
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1CLR  
1D  
1
2
3
4
5
6
7
14 VCC  
13  
12  
11  
10  
9
2CLR  
2D  
•
•
•
•
Operates From 2 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 5.2 ns at 3.3 V  
1CLK  
1PRE  
1Q  
2CLK  
2PRE  
2Q  
Typical VOLP (Output Ground Bounce) <0.8 V at  
VCC = 3.3 V, TA = 25°C  
1Q  
8
GND  
2Q  
•
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVC74A-Q1 dual positive-edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.  
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,  
data at the D input can be changed without affecting the levels at the outputs.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in  
a mixed 3.3-V/5-V system environment.  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2)  
Reel of 2500  
Reel of 2000  
ORDERABLE PART NUMBER  
SN74LVC74AQDRQ1  
TOP-SIDE MARKING  
LVC74AQ  
LVC74AQ  
SOIC – D  
–40°C to 125°C  
TSSOP – PW  
SN74LVC74AQPWRQ1  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2008, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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SN74LVC74A-Q1 替代型号

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