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SCAS299H − JANUARY 1993 − REVISED AUGUST 2003
DB, DW, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
D
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max t of 7 ns at 3.3 V
pd
1
24
23
22
21
20
19
18
17
16
15
14
13
LEBA
OEBA
A1
V
CC
2
CEBA
B1
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
3
= 3.3 V, T = 25°C
A
4
A2
B2
Typical V
(Output V
Undershoot)
OHV
OH
5
A3
B3
>2 V at V
= 3.3 V, T = 25°C
CC
A
6
A4
B4
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
7
A5
B5
8
A6
B6
3.3-V V
)
CC
9
A7
B7
D
D
I
Supports Partial-Power-Down Mode
off
10
11
12
A8
CEAB
GND
B8
LEAB
OEAB
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
description/ordering information
This octal registered transceiver is designed for 1.65-V to 3.6-V V
operation.
CC
The SN74LVC543A contains two sets of D-type latches for temporary storage of data flowing in either direction.
Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each
register to permit independent control in either direction of data flow.
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB places the A
latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the
data present at the output of the A latches. Data flow for B to A is similar to that of A to B, but uses CEBA, LEBA,
and OEBA.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
ORDERING INFORMATION
ORDERABLE
†
T
PACKAGE
TOP-SIDE MARKING
A
PART NUMBER
SN74LVC543ADW
SN74LVC543ADWR
SN74LVC543ADBR
SN74LVC543APW
SN74LVC543APWR
SN74LVC543APWT
Tube of 25
SOIC − DW
SSOP − DB
LVC543A
LC543A
Reel of 2000
Reel of 2000
Tube of 60
−40°C to 85°C
TSSOP − PW
Reel of 2000
Reel of 250
LC543A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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