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SN74LVC544APWR PDF预览

SN74LVC544APWR

更新时间： 2024-11-06 08:55:55
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件
页数 文件大小 规格书
9页 127K
描述
LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, INVERTED OUTPUT, PDSO24, TSSOP-24

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SN74LVC544APWR 数据手册

 浏览型号SN74LVC544APWR的Datasheet PDF文件第2页浏览型号SN74LVC544APWR的Datasheet PDF文件第3页浏览型号SN74LVC544APWR的Datasheet PDF文件第4页浏览型号SN74LVC544APWR的Datasheet PDF文件第5页浏览型号SN74LVC544APWR的Datasheet PDF文件第6页浏览型号SN74LVC544APWR的Datasheet PDF文件第7页 
SN74LVC544A  
OCTAL REGISTERED TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCAS346E – MARCH 1994 – REVISED JUNE 1998  
DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
LEBA  
OEBA  
A1  
1
24  
V
CC  
23 CEBA  
= 3.3 V, T = 25°C  
CC  
A
2
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
3
22 B1  
OHV  
OH  
= 3.3 V, T = 25°C  
CC  
A
A2  
4
21 B2  
A3  
A4  
A5  
5
20 B3  
Power Off Disables Outputs, Permitting  
Live Insertion  
6
19  
18  
17  
16  
15  
14  
13  
B4  
B5  
7
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
8
A6  
A7  
A8  
B6  
B7  
B8  
LEAB  
OEAB  
9
3.3-V V  
)
CC  
10  
11  
12  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages  
CEAB  
GND  
description  
This octal registered transceiver is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74LVC544A contains two sets of D-type latches for temporary storage of data flowing in either direction.  
Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each  
register to permit independent control in either direction of data flow.  
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and  
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB places the A  
latches in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the  
inverted data present at the output of the A latches. Data flow from B to A is similar to A to B, but requires using  
the CEBA, LEBA, and OEBA.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
The SN74LVC544A is characterized for operation from –40°C to 85°C.  
†
FUNCTION TABLE  
INPUTS  
OUTPUT  
B
CEAB  
LEAB  
OEAB  
A
H
L
L
L
L
X
X
H
L
X
H
L
X
X
X
L
Z
Z
‡
B
0
L
H
L
L
L
H
†
‡
A-to-B data flow is shown; B-to-A flow control is the  
same except that it uses CEBA, LEBA, and OEBA.  
Output level before the indicated steady-state input  
conditions were established  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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