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SN74LVC573A

更新时间: 2024-11-04 23:06:23
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德州仪器 - TI 锁存器输出元件
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9页 130K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN74LVC573A 数据手册

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SN54LVC573A, SN74LVC573A  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCAS300I – JANUARY 1993 – REVISED JUNE 1998  
SN54LVC573A . . . J OR W PACKAGE  
SN74LVC573A . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
CC  
A
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
14  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Support Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
3.3-V V  
)
CC  
Power Off Disables Outputs, Permitting  
Live Insertion  
13 7Q  
12 8Q  
11 LE  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
GND 10  
SN54LVC573A . . . FK PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW), and  
Ceramic Flat (W) Packages, Ceramic Chip  
Carriers (FK), and DIPs (J)  
3
2
1 20 19  
18  
2Q  
3Q  
4Q  
5Q  
6Q  
3D  
4D  
5D  
6D  
7D  
4
5
6
7
8
17  
16  
15  
14  
description  
9 10 11 12 13  
TheSN54LVC573AoctaltransparentD-typelatch  
is designed for 2.7-V to 3.6-V V operation and  
CC  
the SN74LVC573A octal transparent D-type latch  
is designed for 1.65-V to 3.6-V V operation.  
CC  
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. They are particularly suitable for implementing buffer registers, input/output (I/O) ports,  
bidirectional bus drivers, and working registers.  
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the  
Q outputs are latched at the logic levels at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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