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SN74LS224AN

更新时间： 2024-11-05 23:06:19
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德州仪器 - TI 存储内存集成电路光电二极管输出元件先进先出芯片
页数 文件大小 规格书
9页 137K
描述
16 】 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS

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SN74LS224AN 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP16,.3针数：16
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.8
最长访问时间：80 nsJESD-30 代码：R-PDIP-T16
长度：19.305 mm内存密度：64 bit
内存集成电路类型：OTHER FIFO内存宽度：4
功能数量：1端子数量：16
字数：16 words字数代码：16
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：16X4
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP16,.3封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
认证状态：Not Qualified座面最大高度：5.08 mm
子类别：FIFOs最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：TTL
温度等级：COMMERCIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：7.62 mm
Base Number Matches：1

SN74LS224AN 数据手册

 浏览型号SN74LS224AN的Datasheet PDF文件第2页浏览型号SN74LS224AN的Datasheet PDF文件第3页浏览型号SN74LS224AN的Datasheet PDF文件第4页浏览型号SN74LS224AN的Datasheet PDF文件第5页浏览型号SN74LS224AN的Datasheet PDF文件第6页浏览型号SN74LS224AN的Datasheet PDF文件第7页 
SN74LS224A  
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY  
WITH 3-STATE OUTPUTS  
SDLS023C – JANUARY 1991 – REVISED DECEMBER 1999  
N PACKAGE  
(TOP VIEW)  
Independent Synchronous Inputs and  
Outputs  
16 Words by 4 Bits Each  
V
OE  
IR  
LDCK  
D0  
D1  
D2  
D3  
GND  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC  
3-State Outputs Drive Bus Lines Directly  
Data Rates up to 10 MHz  
UNCK  
OR  
Q0  
Q1  
Q2  
Fall-Through Time 50 ns Typical  
Data Terminals Arranged for Printed Circuit  
Board Layout  
Q3  
CLR  
Expandable Using External Gating  
Packaged in Standard Plastic 300-mil DIPs  
description  
The SN74LS224A 64-bit, low-power Schottky memory is organized as 16 words by 4 bits each. It can be  
expanded in multiples of 15m + 1 words or 4n bits, or both (where n is the number of packages in the vertical  
array and m is the number of packages in the horizontal array); however, some external gating is required. For  
longer words, the input ready (IR) signals of the first-rank packages and output ready (OR) signals of the  
last-rank packages must be ANDed for proper synchronization.  
A first-in, first-out (FIFO) memory is a storage device that allows data to be written to and read from its array  
at independent data rates. These FIFOs are designed to process data at rates up to 10 MHz in a bit-parallel  
format, word by word.  
The load clock (LDCK) normally is held low, and data is written into memory on the high-to-low transition of  
LDCK. The unload clock (UNCK) normally is held high, and data is read out on the low-to-high transition of  
UNCK. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked  
out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory  
is empty, UNCK signals have no effect.  
Status of the FIFO memory is monitored by the IR and OR flags that indicate not-full and not-empty conditions.  
IR is high only when the memory is not full and LDCK is low. OR is high only when the memory is not empty  
and UNCK is high.  
A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low  
to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting with respect to  
the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the IR  
and OR outputs.  
The SN74LS224A is characterized for operation from 0°C to 70°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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SN74LS224AN 替代型号

型号 品牌 替代类型 描述 数据表
SN54LS224AJ TI

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 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMOR

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