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SN74LS228J PDF预览

SN74LS228J

更新时间: 2024-11-06 21:21:03
品牌 Logo 应用领域
德州仪器 - TI 先进先出芯片内存集成电路
页数 文件大小 规格书
10页 156K
描述
16X4 OTHER FIFO, 80ns, CDIP16

SN74LS228J 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP16,.3Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.71
风险等级:5.92最长访问时间:80 ns
其他特性:FALL-THROUGH TIME 50NS周期时间:100 ns
JESD-30 代码:R-GDIP-T16长度:19.56 mm
内存密度:64 bit内存集成电路类型:OTHER FIFO
内存宽度:4功能数量:1
端子数量:16字数:16 words
字数代码:16工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:16X4可输出:YES
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FIFOs
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

SN74LS228J 数据手册

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SDLS024 − JANUARY 1991 − REVISED SEPTEMBER 1993  
N PACKAGE  
(TOP VIEW)  
Independent Synchronous Inputs and  
Outputs  
16 Words by 4 Bits  
V
OE  
IR  
LDCK  
D0  
D1  
D2  
D3  
GND  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC  
Data Rates From 0 to 10 MHz  
Fall-Through Time . . . 50 ns Typ  
UNCK  
OR  
Q0  
Q1  
Q2  
Q3  
CLR  
Data Terminals Arranged for  
Printed-Circuit-Board Layout  
Expandable Using External Gating  
Packaged in Standard Plastic 300-mil DIPs  
description  
This 64-bit memory is a low-power Schottky memory array organized as 16 words by 4 bits. It can be expanded  
in multiples of 15m + 1 words or 4n bits, or both (where n is the number of packages in the vertical array and  
m is the number of packages in the horizontal array), however some external gating is required (see Figure 1).  
For longer words using the SN74LS228, the IR signals of the first-rank packages and OR signals of the last-rank  
packages must be ANDed for proper synchronization.  
A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array  
at independent data rates. These FIFOs are designed to process data at rates from 0 to 10 MHz in a bit-parallel  
format, word by word.  
Data is written into memory on a low-to-high transition at the load-clock (LDCK) input and is read out on a  
low-to-high transition at the unload-clock (UNCK) input. The memory is full when the number of words clocked  
in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect on  
the data residing in memory. When the memory is empty, UNCK signals have no effect.  
Status of the FIFO memory is monitored by the input-ready (IR) and output-ready (OR) flags that indicate not-full  
and not-empty conditions. IR is high only when the memory is not full and the LDCK is low. OR is high only when  
the memory is not empty and UNCK is high.  
A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low  
to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting with respect to  
the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the IR  
and OR outputs.  
The SN74LS228 is characterized for operation from 0°C to 70°C.  
ꢒꢦ  
Copyright 1993, Texas Instruments Incorporated  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
10−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS  
77251−1443  

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