Datasheet > 存储 > FIFO> SN74LS228

SN74LS228

更新时间： 2024-09-16 09:14:03

品牌	Logo	应用领域
德州仪器 - TI		存储输出元件
页数	文件大小	规格书
10页	149K
描述
16 x 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS

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SN74LS228 数据手册

SN74LS228

16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY

WITH OPEN-COLLECTOR OUTPUTS

SDLS024 – JANUARY 1991 – REVISED SEPTEMBER 1993

N PACKAGE

(TOP VIEW)

• Independent Synchronous Inputs and

Outputs

• 16 Words by 4 Bits

• Data Rates From 0 to 10 MHz

• Fall-Through Time . . . 50 ns Typ

LDCK

GND

UNCK

• Data Terminals Arranged for

Printed-Circuit-Board Layout

• Expandable Using External Gating

• Packaged in Standard Plastic 300-mil DIPs

CLR

description

This 64-bit memory is a low-power Schottky memory array organized as 16 words by 4 bits. It can be expanded

in multiples of 15m + 1 words or 4n bits, or both (where n is the number of packages in the vertical array and

m is the number of packages in the horizontal array), however some external gating is required (see Figure 1).

For longer words using the SN74LS228, the IR signals of the first-rank packages and OR signals of the last-rank

packages must be ANDed for proper synchronization.

A first-in, first-out (FIFO) memory is a storage device that allows data to be written into and read from its array

at independent data rates. These FIFOs are designed to process data at rates from 0 to 10 MHz in a bit-parallel

format, word by word.

Data is written into memory on a low-to-high transition at the load-clock (LDCK) input and is read out on a

low-to-high transition at the unload-clock (UNCK) input. The memory is full when the number of words clocked

in exceeds by 16 the number of words clocked out. When the memory is full, LDCK signals have no effect on

the data residing in memory. When the memory is empty, UNCK signals have no effect.

Status of the FIFO memory is monitored by the input-ready (IR) and output-ready (OR) flags that indicate not-full

and not-empty conditions. IR is high only when the memory is not full and the LDCK is low. OR is high only when

the memory is not empty and UNCK is high.

A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low

to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting with respect to

the data inputs and are at high impedance when the output-enable (OE) input is low. OE does not affect the IR

and OR outputs.

The SN74LS228 is characterized for operation from 0°C to 70°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

10–1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...10

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与SN74LS228相关器件

型号	品牌	获取价格	描述	数据表
SN74LS228J	TI	获取价格	16X4 OTHER FIFO, 80ns, CDIP16
SN74LS228J4	TI	获取价格	IC IC,FIFO,16X4,ASYNCHRONOUS,LS-TTL,DIP,16PIN,CERAMIC, FIFO
SN74LS228JP4	TI	获取价格	暂无描述
SN74LS228N	TI	获取价格	16 x 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH OPEN-COLLECTOR OUTPUTS
SN74LS228N3	TI	获取价格	IC IC,FIFO,16X4,ASYNCHRONOUS,LS-TTL,DIP,16PIN,PLASTIC, FIFO
SN74LS228NP1	TI	获取价格	IC,FIFO,16X4,ASYNCHRONOUS,LS-TTL,DIP,16PIN,PLASTIC
SN74LS228NP3	TI	获取价格	IC IC,FIFO,16X4,ASYNCHRONOUS,LS-TTL,DIP,16PIN,PLASTIC, FIFO
SN74LS22D	MOTOROLA	获取价格	DUAL 4-INPUT NAND GATE
SN74LS22D3	ROCHESTER	获取价格	NAND Gate
SN74LS22DR	TI	获取价格	LS SERIES, DUAL 4-INPUT NAND GATE, PDSO14

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