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SN54LS224AJ PDF预览

SN54LS224AJ

更新时间： 2024-11-20 02:58:39
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德州仪器 - TI 输出元件
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13页 355K
描述
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES WITH 3-STATE OUTPUTS

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SN54LS224AJ 数据手册

 浏览型号SN54LS224AJ的Datasheet PDF文件第2页浏览型号SN54LS224AJ的Datasheet PDF文件第3页浏览型号SN54LS224AJ的Datasheet PDF文件第4页浏览型号SN54LS224AJ的Datasheet PDF文件第5页浏览型号SN54LS224AJ的Datasheet PDF文件第6页浏览型号SN54LS224AJ的Datasheet PDF文件第7页 
SN54LS224A, SN74LS224A  
16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES  
WITH 3-STATE OUTPUTS  
SDLS023E – JANUARY 1991 – REVISED APRIL 2003  
SN54LS224A . . . J PACKAGE  
SN74LS224A . . . N PACKAGE  
(TOP VIEW)  
Independent Synchronous Inputs and  
Outputs  
16 Words by 4 Bits Each  
3-State Outputs Drive Bus Lines Directly  
Data Rates up to 10 MHz  
Fall-Through Time 50 ns Typical  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
OE  
IR  
LDCK  
D0  
D1  
D2  
D3  
GND  
CC  
UNCK  
OR  
Q0  
Q1  
Q2  
Q3  
CLR  
Data Terminals Arranged for Printed Circuit  
Board Layout  
Expandable, Using External Gating  
Packaged in Standard Plastic (N) and  
Ceramic (J) 300-mil DIPs, and Ceramic Chip  
Carriers (FK)  
SN54LS224A . . . FK PACKAGE  
(TOP VIEW)  
description  
The SN54LS224A and SN74LS224A 64-bit,  
low-power Schottky memories are organized as  
16 words by 4 bits each. They can be expanded  
in multiples of 15m + 1 words or 4n bits, or both  
(where n is the number of packages in the vertical  
array and m is the number of packages in the  
horizontal array); however, some external gating  
is required. For longer words, the input-ready (IR)  
signals of the first-rank packages and  
output-ready (OR) signals of the last-rank  
packages must be ANDed for proper  
synchronization.  
3
9
2
1
20 19  
18  
LDCK  
D0  
OR  
Q0  
NC  
Q1  
Q2  
4
5
6
7
8
17  
16  
15  
14  
NC  
D1  
D2  
10 11 12 13  
NC – No internal connection  
A first-in, first-out (FIFO) memory is a storage  
device that allows data to be written to and read  
from its array at independent data rates. These  
FIFOs are designed to process data at rates up to  
10 MHz in a bit-parallel format, word by word.  
The load clock (LDCK) normally is held low, and data is written into memory on the high-to-low transition of  
LDCK. The unload clock (UNCK) normally is held high, and data is read out on the low-to-high transition of  
UNCK. The memory is full when the number of words clocked in exceeds by 16 the number of words clocked  
out. When the memory is full, LDCK signals have no effect on the data residing in memory. When the memory  
is empty, UNCK signals have no effect.  
Status of the FIFO memory is monitored by the IR and OR flags that indicate not-full and not-empty conditions.  
IR is high only when the memory is not full and LDCK is low. OR is high only when the memory is not empty  
and UNCK is high.  
A low level on the clear (CLR) input resets the internal stack-control pointers and also sets IR high and OR low  
to indicate that old data remaining at the data outputs is invalid. Data outputs are noninverting, with respect to  
the data inputs, and are at high impedance when the output-enable (OE) input is low. OE does not affect the  
IR and OR outputs.  
The SN74LS224A is characterized for operation from 0°C to 70°C. The SN54LS224A is characterized over the  
full military temperature range of –55°C to 125°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
unless otherwise noted. On all other products, production  
testing of all parameters.  
processing does not necessarily include testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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SN54LS224AJ 替代型号

型号 品牌 替代类型 描述 数据表
SNJ54LS224AJ TI

完全替代

 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMOR
SN74LS224AN3 TI

功能相似

 16 × 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMOR
SN74LS224AN TI

功能相似

 16 】 4 SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY

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