SN74GTLP1395DGV

更新时间： 2024-11-25 22:53:35

品牌	Logo	应用领域
德州仪器 - TI		总线收发器
页数	文件大小	规格书
21页	440K
描述
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY

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SN74GTLP1395DGV 数据手册

SN74GTLP1395

TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS

WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY

SCES349C – JUNE 2001 – REVISED NOVEMBER 2001

DGV, DW, OR PW PACKAGE

TI-OPC Circuitry Limits Ringing on

Unevenly Loaded Backplanes

(TOP VIEW)

OEC Circuitry Improves Signal Integrity

and Reduces Electromagnetic Interference

1T/C

1OEBY

2T/C

2OEBY

GND

ERC

GND

Bidirectional Interface Between GTLP

Signal Levels and LVTTL Logic Levels

GND

1OEAB

Split LVTTL Port Provides a Feedback Path

for Control and Diagnostics Monitoring

GND

2OEAB

LVTTL Interfaces Are 5-V Tolerant

High-Drive GTLP Outputs (100 mA)

LVTTL Outputs (–24 mA/24 mA)

REF

BIAS V

Variable Edge-Rate Control (ERC) Input

Selects GTLP Rise and Fall Times for

Optimal Data-Transfer Rate and Signal

Integrity in Distributed Loads

, Power-Up 3-State, and BIAS V

off

Support Live Insertion

Polarity Control Selects True or

Complementary Outputs

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

description

The SN74GTLP1395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and

GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require

individual output-enable and true/complement controls. The device allows for transparent and inverted

transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback

path for control and diagnostics monitoring. The device provides a high-speed interface between cards

operating at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to

work with the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times

faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V),

reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved

GTLP OEC and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several

backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent

load impedance down to 11 Ω.

GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.

The ac specification of the SN74GTLP1395 is given only at the preferred higher noise margin GTLP, but the

user has the flexibility of using this device at either GTL (V = 1.2 V and V

= 0.8 V) or GTLP (V = 1.5 V

REF

and V

= 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI

REF

application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and

GTLP in BTL Applications, literature number SCEA017.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

OEC and TI-OPC are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...21

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与SN74GTLP1395DGV相关器件

型号	品牌	获取价格	描述	数据表
SN74GTLP1395DGVR	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395DW	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395DWE4	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395DWR	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395DWRE4	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395DWRG4	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
SN74GTLP1395GQNR	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395PW	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395PWE4	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395PWG4	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS

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