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SN74GTLP2034DGGR PDF预览

SN74GTLP2034DGGR

更新时间： 2024-11-26 04:31:15
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
21页 435K
描述
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND FEEDBACK PATH

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SN74GTLP2034DGGR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP-48
针数：48Reach Compliance Code：unknown
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：8.6Is Samacsys：N
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：GTLPJESD-30 代码：R-PDSO-G48
长度：12.5 mm逻辑集成电路类型：REGISTERED BUS TRANSCEIVER
最大I（ol）：0.1 A位数：8
功能数量：1端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：OPEN-DRAIN/3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V最大电源电流（ICC）：40 mA
Prop。Delay @ Nom-Sup：7.1 ns传播延迟（tpd）：8.6 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：GTLP & LVTTL
触发器类型：POSITIVE EDGE宽度：6.1 mm
Base Number Matches：1

SN74GTLP2034DGGR 数据手册

 浏览型号SN74GTLP2034DGGR的Datasheet PDF文件第2页浏览型号SN74GTLP2034DGGR的Datasheet PDF文件第3页浏览型号SN74GTLP2034DGGR的Datasheet PDF文件第4页浏览型号SN74GTLP2034DGGR的Datasheet PDF文件第5页浏览型号SN74GTLP2034DGGR的Datasheet PDF文件第6页浏览型号SN74GTLP2034DGGR的Datasheet PDF文件第7页 
SN74GTLP2034  
8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER  
WITH SPLIT LVTTL PORT AND FEEDBACK PATH  
SCES353C – JUNE 2001 – REVISED SEPTEMBER 2001  
DGG OR DGV PACKAGE  
Member of the Texas Instruments  
Widebus Family  
(TOP VIEW)  
TI-OPC Circuitry Limits Ringing on  
Unevenly Loaded Backplanes  
IMODE1  
AI1  
IMODE0  
BIAS V  
B1  
GND  
OEAB  
B2  
ERC  
OEAB  
B3  
1
2
3
4
5
6
7
8
9
48  
47  
46  
45  
44  
43  
42  
41  
40  
CC  
OEC Circuitry Improves Signal Integrity  
and Reduces Electromagnetic Interference  
AO1  
GND  
AI2  
Bidirectional Interface Between GTLP  
Signal Levels and LVTTL Logic Levels  
AO2  
V
Split LVTTL Port Provides a Feedback Path  
for Control and Diagnostics Monitoring  
CC  
AI3  
AO3  
LVTTL Interfaces Are 5-V Tolerant  
GND 10  
AI4  
39 GND  
High-Drive GTLP Open-Drain Outputs  
(100 mA)  
CLKAB/LEAB  
B4  
11  
12  
38  
37  
AO4  
LVTTL Outputs (–24 mA/24 mA)  
AO5 13  
AI5 14  
36 B5  
Variable Edge-Rate Control (ERC) Input  
Selects GTLP Rise and Fall Times for  
Optimal Data-Transfer Rate and Signal  
Integrity in Distributed Loads  
35 CLKBA/LEBA  
34 GND  
GND 15  
AO6 16  
AI6 17  
33 B6  
32 OEBA  
V
18  
31  
V
I
, Power-Up 3-State, and BIAS V  
CC  
CC  
CC  
off  
AO7 19  
30 B7  
Support Live Insertion  
AI7 20  
29 LOOPBACK  
28 GND  
27 B8  
Distributed V and GND Pins Minimize  
High-Speed Switching Noise  
CC  
GND 21  
AO8 22  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
AI8 23  
26  
V
REF  
OMODE0 24  
25 OMODE1  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
description  
The SN74GTLP2034 is a high-drive, 8-bit, three-wire registered transceiver that provides true LVTTL-to-GTLP  
and GTLP-to-LVTTL signal-level translation. The device allows for transparent, latched, and flip-flop modes of  
data transfer with separate LVTTL input and LVTTL output pins, which provides a feedback path for control and  
diagnostics monitoring, the same functionality as the SN74FB2033, but with true logic. The device provides a  
high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal  
levels. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result  
of GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC  
circuitry, and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have  
been designed and tested using several backplane models. The high drive allows incident-wave switching in  
heavily loaded backplanes with equivalent load impedance down to 11 Ω.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
OEC, TI-OPC, and Widebus are trademarks of Texas Instruments.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

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