5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74GTLP1395DWRE4
SN74GTLP1395DWRE4 PDF预览

SN74GTLP1395DWRE4

更新时间： 2024-11-25 22:53:35
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
21页 440K
描述
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY

阅读下载

中文翻译

获取价格

SN74GTLP1395DWRE4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：SOP, SOP20,.4针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.61Is Samacsys：N
控制类型：INDEPENDENT CONTROL计数方向：BIDIRECTIONAL
系列：GTLPJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：12.8 mm
逻辑集成电路类型：BUS TRANSCEIVER最大I（ol）：0.1 A
湿度敏感等级：1位数：1
功能数量：2端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：CONFIGURABLE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：20 mA
传播延迟（tpd）：6.3 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.45 V最小供电电压 (Vsup)：3.15 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：GTLP & LVTTL
宽度：7.5 mmBase Number Matches：1

SN74GTLP1395DWRE4 数据手册

 浏览型号SN74GTLP1395DWRE4的Datasheet PDF文件第2页浏览型号SN74GTLP1395DWRE4的Datasheet PDF文件第3页浏览型号SN74GTLP1395DWRE4的Datasheet PDF文件第4页浏览型号SN74GTLP1395DWRE4的Datasheet PDF文件第5页浏览型号SN74GTLP1395DWRE4的Datasheet PDF文件第6页浏览型号SN74GTLP1395DWRE4的Datasheet PDF文件第7页 
SN74GTLP1395  
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS  
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY  
SCES349C – JUNE 2001 – REVISED NOVEMBER 2001  
DGV, DW, OR PW PACKAGE  
TI-OPC Circuitry Limits Ringing on  
Unevenly Loaded Backplanes  
(TOP VIEW)  
OEC Circuitry Improves Signal Integrity  
and Reduces Electromagnetic Interference  
1Y  
1T/C  
2Y  
1OEBY  
2T/C  
2OEBY  
GND  
1B  
ERC  
2B  
GND  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Bidirectional Interface Between GTLP  
Signal Levels and LVTTL Logic Levels  
GND  
1OEAB  
Split LVTTL Port Provides a Feedback Path  
for Control and Diagnostics Monitoring  
V
CC  
1A  
GND  
2A  
2OEAB  
LVTTL Interfaces Are 5-V Tolerant  
High-Drive GTLP Outputs (100 mA)  
LVTTL Outputs (–24 mA/24 mA)  
V
REF  
BIAS V  
CC  
Variable Edge-Rate Control (ERC) Input  
Selects GTLP Rise and Fall Times for  
Optimal Data-Transfer Rate and Signal  
Integrity in Distributed Loads  
I
, Power-Up 3-State, and BIAS V  
CC  
off  
Support Live Insertion  
Polarity Control Selects True or  
Complementary Outputs  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
description  
The SN74GTLP1395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and  
GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require  
individual output-enable and true/complement controls. The device allows for transparent and inverted  
transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback  
path for control and diagnostics monitoring. The device provides a high-speed interface between cards  
operating at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to  
work with the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times  
faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V),  
reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved  
GTLP OEC and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several  
backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent  
load impedance down to 11 Ω.  
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.  
The ac specification of the SN74GTLP1395 is given only at the preferred higher noise margin GTLP, but the  
user has the flexibility of using this device at either GTL (V = 1.2 V and V  
= 0.8 V) or GTLP (V = 1.5 V  
TT  
REF  
TT  
and V  
= 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI  
REF  
application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and  
GTLP in BTL Applications, literature number SCEA017.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
OEC and TI-OPC are trademarks of Texas Instruments.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

中文翻译

下载PDF

与SN74GTLP1395DWRE4相关器件

型号 品牌 获取价格 描述 数据表
SN74GTLP1395DWRG4 TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
SN74GTLP1395GQNR TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395PW TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395PWE4 TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395PWG4 TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
SN74GTLP1395PWR TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395PWRE4 TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395PWRG4 TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
SN74GTLP2033 TI

获取价格

 		8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND
SN74GTLP2033DGGR TI

获取价格

 		8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND

与SN74GTLP1395DWRE4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证