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SN74GTLP21395DWR

更新时间： 2024-11-26 04:31:15
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德州仪器 - TI 总线收发器
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21页 435K
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TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY

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SN74GTLP21395DWR 数据手册

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SN74GTLP21395  
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS  
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY  
SCES350C – JUNE 2001 – REVISED NOVEMBER 2001  
DGV, DW, OR PW PACKAGE  
TI-OPC Circuitry Limits Ringing on  
Unevenly Loaded Backplanes  
(TOP VIEW)  
OEC Circuitry Improves Signal Integrity  
and Reduces Electromagnetic Interference  
1Y  
1T/C  
2Y  
1OEBY  
2T/C  
2OEBY  
GND  
1B  
ERC  
2B  
GND  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
Bidirectional Interface Between GTLP  
Signal Levels and LVTTL Logic Levels  
GND  
1OEAB  
Split LVTTL Port Provides a Feedback Path  
for Control and Diagnostics Monitoring  
V
CC  
1A  
GND  
2A  
2OEAB  
Y Outputs Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
V
REF  
BIAS V  
CC  
LVTTL Interfaces Are 5-V Tolerant  
High-Drive GTLP Outputs (100 mA)  
LVTTL Outputs (–12 mA/12 mA)  
Variable Edge-Rate Control (ERC) Input  
Selects GTLP Rise and Fall Times for  
Optimal Data-Transfer Rate and Signal  
Integrity in Distributed Loads  
I
, Power-Up 3-State, and BIAS V  
CC  
off  
Support Live Insertion  
Polarity Control Selects True or  
Complementary Outputs  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
description  
The SN74GTLP21395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and  
GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require  
individual output-enable and true/complement controls. The device allows for transparent and inverted  
transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback  
path for control and diagnostics monitoring. The device provides a high-speed interface between cards  
operating at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to  
work with the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times  
faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V),  
reduced input threshold levels, improved differential input, OEC circuitry, and TI-OPC circuitry. Improved  
GTLP OEC and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several  
backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent  
load impedance down to 11 Ω.  
The Y outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot  
and undershoot.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
OEC and TI-OPC are trademarks of Texas Instruments.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

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