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Datasheet > SN74GTLP21395PWE4
SN74GTLP21395PWE4 PDF预览

SN74GTLP21395PWE4

更新时间： 2024-11-26 15:52:11
品牌 Logo 应用领域
德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
26页 1139K
描述
GTLP SERIES, DUAL 1-BIT TRANSCEIVER, CONFIGURABLE OUTPUT, PDSO20, GREEN, PLASTIC,TSSOP-20

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SN74GTLP21395PWE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20,.25针数：20
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.65控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：GTLP
JESD-30 代码：R-PDSO-G20长度：6.5 mm
逻辑集成电路类型：BUS TRANSCEIVER最大I（ol）：0.1 A
位数：1功能数量：2
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：CONFIGURABLE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
最大电源电流（ICC）：20 mA传播延迟（tpd）：10.4 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.45 V
最小供电电压 (Vsup)：3.15 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：GTLP & LVTTL
宽度：4.4 mmBase Number Matches：1

SN74GTLP21395PWE4 数据手册

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SN74GTLP21395  
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS  
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY  
www.ti.com  
SCES350C–JUNE 2001–REVISED DECEMBER 2005  
FEATURES  
•
•
•
Polarity Control Selects True or  
Complementary Outputs  
•
•
•
•
•
TI-OPC™ Circuitry Limits Ringing on  
Unevenly Loaded Backplanes  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
OEC™ Circuitry Improves Signal Integrity and  
Reduces Electromagnetic Interference  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Bidirectional Interface Between GTLP Signal  
Levels and LVTTL Logic Levels  
Split LVTTL Port Provides a Feedback Path  
for Control and Diagnostics Monitoring  
– 1000-V Charged-Device Model (C101)  
DGV, DW, OR PW PACKAGE  
(TOP VIEW)  
Y Outputs Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
1Y  
1T/C  
1OEBY  
2T/C  
2OEBY  
GND  
1B  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
•
•
•
•
LVTTL Interfaces Are 5-V Tolerant  
High-Drive GTLP Outputs (100 mA)  
LVTTL Outputs (–12 mA/12 mA)  
2Y  
GND  
1OEAB  
Variable Edge-Rate Control (ERC) Input  
Selects GTLP Rise and Fall Times for Optimal  
Data-Transfer Rate and Signal Integrity in  
Distributed Loads  
V
CC  
ERC  
2B  
1A  
GND  
2A  
GND  
V
REF  
•
Ioff, Power-Up 3-State, and BIAS VCC Support  
Live Insertion  
2OEAB  
BIAS V  
CC  
DESCRIPTION/ORDERING INFORMATION  
The SN74GTLP21395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and  
GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require  
individual output-enable and true/complement controls. The device allows for transparent and inverted  
transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback  
path for control and diagnostics monitoring. The device provides a high-speed interface between cards operating  
at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to work with  
the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times faster than  
standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced  
input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC  
and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several backplane  
models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent load  
impedance down to 11 Ω.  
The Y outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot  
and undershoot.  
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.  
The ac specification of the SN74GTLP21395 is given only at the preferred higher noise margin GTLP, but the  
user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and  
VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI application  
reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and GTLP in BTL  
Applications, literature number SCEA017.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TI-OPC, OEC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2001–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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SN74GTLP21395PWE4 替代型号

型号 品牌 替代类型 描述 数据表
SN74GTLP21395PWR TI

完全替代

 TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB

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