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SN74GTLP817DWE4 PDF预览

SN74GTLP817DWE4

更新时间: 2024-11-28 04:31:15
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
19页 287K
描述
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER

SN74GTLP817DWE4 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:GREEN, PLASTIC, SOIC-24针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.77Is Samacsys:N
其他特性:GTLP-TO-LVTTL DIRECTION IS A 1-TO-6 FANOUT DRIVER; LVTTL-TO-GTLP DIRECTION IS A 1-TO-2 FANOUT DRIVER系列:GTLP
JESD-30 代码:R-PDSO-G24长度:15.4 mm
逻辑集成电路类型:BUS DRIVER位数:1
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):6 ns认证状态:Not Qualified
座面最大高度:2.65 mm最大供电电压 (Vsup):3.45 V
最小供电电压 (Vsup):3.15 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

SN74GTLP817DWE4 数据手册

 浏览型号SN74GTLP817DWE4的Datasheet PDF文件第2页浏览型号SN74GTLP817DWE4的Datasheet PDF文件第3页浏览型号SN74GTLP817DWE4的Datasheet PDF文件第4页浏览型号SN74GTLP817DWE4的Datasheet PDF文件第5页浏览型号SN74GTLP817DWE4的Datasheet PDF文件第6页浏览型号SN74GTLP817DWE4的Datasheet PDF文件第7页 
SN74GTLP817  
GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER  
www.ti.com  
SCES285EOCTOBER 1999REVISED APRIL 2005  
FEATURES  
DGV, DW, OR PW PACKAGE  
(TOP VIEW)  
OEC™ Circuitry Improves Signal Integrity and  
Reduces Electromagnetic Interference  
AI  
AO1  
GNDT  
OEAB  
1
2
3
4
5
6
7
8
9
24  
23  
Bidirectional Interface Between GTLP Signal  
Levels and LVTTL Logic Levels  
GNDT  
AO2  
22 BO1  
GTLP-to-LVTTL 1-to-6 Fanout Driver  
LVTTL-to-GTLP 1-to-2 Fanout Driver  
LVTTL Interfaces Are 5-V Tolerant  
Medium-Drive GTLP Outputs (50 mA)  
GNDG  
21  
20  
19  
18  
V
CC  
V
REF  
AO3  
GNDT  
AO4  
GNDG  
ERC  
17 BO2  
16 GNDG  
15 BI  
Reduced-Drive LVTTL Outputs  
(–12 mA/12 mA)  
V
CC  
AO5 10  
GNDT  
AO6  
Variable Edge-Rate Control (ERC) Input  
Selects GTLP Rise and Fall Times for Optimal  
Data-Transfer Rate and Signal Integrity in  
Distributed Loads  
OEBA  
GNDT  
11  
12  
14  
13  
Ioff and Power-Up 3-State Support Hot  
Insertion  
Distributed VCC and GND Pins Minimize  
High-Speed Switching Noise  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
The SN74GTLP817 is a medium-drive fanout driver that provides LVTTL-to-GTLP and GTLP-to-LVTTL  
signal-level translation. The device provides a high-speed interface between cards operating at LVTTL logic  
levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL  
or LVTTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input threshold  
levels, improved differential input, and OEC™ circuitry. The improved GTLP OEC circuitry minimizes bus settling  
time and has been designed and tested using several backplane models. The medium drive allows incident-wave  
switching in heavily loaded backplanes with equivalent load impedance down to 19 . BO1 and BO2 can be tied  
together to drive an equivalent load impedance down to 11 .  
GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard  
JESD 8-3. The ac specification of the SN74GTLP817 is given only at the preferred higher noise-margin GTLP,  
but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP  
(VTT = 1.5 V and VREF = 1 V) signal levels.  
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,  
but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input  
reference voltage.  
GNDT is the TTL output ground, while GNDG is the GTLP output ground, and both may be separated from each  
other for a quieter device.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
OEC, TI are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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