Datasheet > SN74GTLP1395DWRG4

SN74GTLP1395DWRG4

更新时间： 2024-11-26 12:15:03

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德州仪器 - TI		总线收发器
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TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS

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SN74GTLP1395

TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS

WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY

www.ti.com

SCES349C–JUNE 2001–REVISED JANUARY 2006

FEATURES

•

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

•

TI-OPC™ Circuitry Limits Ringing on

Unevenly Loaded Backplanes

OEC™ Circuitry Improves Signal Integrity and

Reduces Electromagnetic Interference

Bidirectional Interface Between GTLP Signal

Levels and LVTTL Logic Levels

Split LVTTL Port Provides a Feedback Path

for Control and Diagnostics Monitoring

– 1000-V Charged-Device Model (C101)

DGV, DW, OR PW PACKAGE

(TOP VIEW)

1T/C

1OEBY

2T/C

2OEBY

GND

ERC

GND

•

LVTTL Interfaces Are 5-V Tolerant

High-Drive GTLP Outputs (100 mA)

LVTTL Outputs (–24 mA/24 mA)

Variable Edge-Rate Control (ERC) Input

Selects GTLP Rise and Fall Times for Optimal

Data-Transfer Rate and Signal Integrity in

Distributed Loads

GND

1OEAB

GND

REF

2OEAB

BIAS V

•

I_off, Power-Up 3-State, and BIAS V_CCSupport

Live Insertion

Polarity Control Selects True or

Complementary Outputs

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

DESCRIPTION/ORDERING INFORMATION

The SN74GTLP1395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and

GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require

individual output-enable and true/complement controls. The device allows for transparent and inverted

transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback

path for control and diagnostics monitoring. The device provides a high-speed interface between cards operating

at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to work with

the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times faster than

standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced

input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC

and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several backplane

models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent load

impedance down to 11 Ω.

GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.

The ac specification of the SN74GTLP1395 is given only at the preferred higher noise margin GTLP, but the user

has the flexibility of using this device at either GTL (V_TT= 1.2 V and V_REF= 0.8 V) or GTLP (V_TT= 1.5 V and

V_REF= 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI application

reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and GTLP in BTL

Applications, literature number SCEA017.

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,

but are 5-V tolerant and are compatible with TTL or 5-V CMOS devices. V_REFis the B-port differential input

reference voltage.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI-OPC, OEC are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...24

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与SN74GTLP1395DWRG4相关器件

型号	品牌	获取价格	描述	数据表
SN74GTLP1395GQNR	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395PW	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395PWE4	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395PWG4	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
SN74GTLP1395PWR	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395PWRE4	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395PWRG4	TI	获取价格	TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
SN74GTLP2033	TI	获取价格	8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND
SN74GTLP2033DGGR	TI	获取价格	8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND
SN74GTLP2033DGVR	TI	获取价格	8-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE REGISTERED TRANSCEIVER WITH SPLIT LVTTL PORT AND

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