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SN74GTLP1394_07

更新时间： 2024-11-26 04:31:15
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德州仪器 - TI /
页数 文件大小 规格书
25页 741K
描述
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY

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SN74GTLP1394_07 数据手册

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SN74GTLP1394  
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER  
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY  
www.ti.com  
SCES286F–OCTOBER 1999–REVISED APRIL 2005  
FEATURES  
Data-Transfer Rate and Signal Integrity in  
Distributed Loads  
•
•
•
•
TI-OPC™ Circuitry Limits Ringing on  
Unevenly Loaded Backplanes  
•
•
•
•
Ioff, Power-Up 3-State, and BIAS VCC Support  
Live Insertion  
OEC™ Circuitry Improves Signal Integrity and  
Reduces Electromagnetic Interference  
Polarity Control Selects True or  
Complementary Outputs  
Bidirectional Interface Between GTLP Signal  
Levels and LVTTL Logic Levels  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Split LVTTL Port Provides a Feedback Path  
for Control and Diagnostics Monitoring  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
•
•
•
LVTTL Interfaces Are 5-V Tolerant  
High-Drive GTLP Outputs (100 mA)  
LVTTL Outputs (–24 mA/24 mA)  
– 1000-V Charged-Device Model (C101)  
Variable Edge-Rate Control (ERC) Input  
Selects GTLP Rise and Fall Times for Optimal  
RGY PACKAGE  
(TOP VIEW)  
D, DGV, OR PW PACKAGE  
(TOP VIEW)  
OEBY  
Y1  
BIAS V  
GND  
B1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
CC  
Y2  
1
16  
V
CC  
GND  
15  
14  
13  
12  
11  
10  
Y1  
Y2  
2
3
4
5
6
7
GND  
B1  
GND  
B2  
A1  
A2  
12 B2  
11  
10  
9
GND  
V
CC  
OEAB  
ERC  
V
REF  
A1  
A2  
OEAB  
T/C  
GND  
V
REF  
8
9
DESCRIPTION/ORDERING INFORMATION  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74GTLP1394RGYR  
SN74GTLP1394D  
TOP-SIDE MARKING  
QFN – RGY  
SOIC – D  
Tape and reel  
GP1394  
Tube  
GTLP1394  
–40°C to 85°C  
Tape and reel  
Tape and reel  
Tape and reel  
SN74GTLP1394DR  
TSSOP – PW  
TVSOP – DGV  
SN74GTLP1394PWR  
SN74GTLP1394DGVR  
GP394  
GP394  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TI-OPC, OEC, TI are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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与SN74GTLP1394_07相关器件

型号 品牌 获取价格 描述 数据表
SN74GTLP1394D TI

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 		2-BIT LVTTL-TO-GTL ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY
SN74GTLP1394DE4 TI

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 		2-Bit LVTTL-to-GTLP Adj-Edge-Rate Bus Xcvr w/Split LVTTL Port, Feedback Path, & Se
SN74GTLP1394DG4 TI

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 		GTLP SERIES, 2-BIT TRANSCEIVER, CONFIGURABLE OUTPUT, PDSO16, GREEN, PLASTIC, MS-012AC, SOI
SN74GTLP1394DGV TI

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 		2-BIT LVTTL-TO-GTL ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY
SN74GTLP1394DGVR TI

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 		2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK P
SN74GTLP1394DR TI

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 		2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK P
SN74GTLP1394DRE4 TI

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 		GTLP SERIES, 2-BIT TRANSCEIVER, CONFIGURABLE OUTPUT, PDSO16, GREEN, PLASTIC, MS-012AC, SOI
SN74GTLP1394PW TI

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 		2-BIT LVTTL-TO-GTL ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY
SN74GTLP1394PWE4 TI

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 		GTLP SERIES, 2-BIT TRANSCEIVER, CONFIGURABLE OUTPUT, PDSO16, GREEN, PLASTIC, TSSOP-16
SN74GTLP1394PWR TI

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 		2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK P

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