5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74GTLP1394RGYR
SN74GTLP1394RGYR PDF预览

SN74GTLP1394RGYR

更新时间： 2024-11-26 04:31:15
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
25页 741K
描述
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY

阅读下载

中文翻译

获取价格

SN74GTLP1394RGYR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFN
包装说明：HVQCCN, LCC16/20,.14X.16,20针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.8系列：GTLP
JESD-30 代码：R-PQCC-N16长度：4 mm
逻辑集成电路类型：BUS TRANSCEIVER位数：2
功能数量：1端口数量：3
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：CONFIGURABLE封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装等效代码：LCC16/20,.14X.16,20
封装形状：RECTANGULAR封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
传播延迟（tpd）：9 ns认证状态：Not Qualified
座面最大高度：1 mm子类别：Other Logic ICs
最大供电电压 (Vsup)：3.45 V最小供电电压 (Vsup)：3.15 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.5 mm

SN74GTLP1394RGYR 数据手册

 浏览型号SN74GTLP1394RGYR的Datasheet PDF文件第2页浏览型号SN74GTLP1394RGYR的Datasheet PDF文件第3页浏览型号SN74GTLP1394RGYR的Datasheet PDF文件第4页浏览型号SN74GTLP1394RGYR的Datasheet PDF文件第5页浏览型号SN74GTLP1394RGYR的Datasheet PDF文件第6页浏览型号SN74GTLP1394RGYR的Datasheet PDF文件第7页 
SN74GTLP1394  
2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER  
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY  
www.ti.com  
SCES286F–OCTOBER 1999–REVISED APRIL 2005  
FEATURES  
Data-Transfer Rate and Signal Integrity in  
Distributed Loads  
•
•
•
•
TI-OPC™ Circuitry Limits Ringing on  
Unevenly Loaded Backplanes  
•
•
•
•
Ioff, Power-Up 3-State, and BIAS VCC Support  
Live Insertion  
OEC™ Circuitry Improves Signal Integrity and  
Reduces Electromagnetic Interference  
Polarity Control Selects True or  
Complementary Outputs  
Bidirectional Interface Between GTLP Signal  
Levels and LVTTL Logic Levels  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Split LVTTL Port Provides a Feedback Path  
for Control and Diagnostics Monitoring  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
•
•
•
LVTTL Interfaces Are 5-V Tolerant  
High-Drive GTLP Outputs (100 mA)  
LVTTL Outputs (–24 mA/24 mA)  
– 1000-V Charged-Device Model (C101)  
Variable Edge-Rate Control (ERC) Input  
Selects GTLP Rise and Fall Times for Optimal  
RGY PACKAGE  
(TOP VIEW)  
D, DGV, OR PW PACKAGE  
(TOP VIEW)  
OEBY  
Y1  
BIAS V  
GND  
B1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
CC  
Y2  
1
16  
V
CC  
GND  
15  
14  
13  
12  
11  
10  
Y1  
Y2  
2
3
4
5
6
7
GND  
B1  
GND  
B2  
A1  
A2  
12 B2  
11  
10  
9
GND  
V
CC  
OEAB  
ERC  
V
REF  
A1  
A2  
OEAB  
T/C  
GND  
V
REF  
8
9
DESCRIPTION/ORDERING INFORMATION  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74GTLP1394RGYR  
SN74GTLP1394D  
TOP-SIDE MARKING  
QFN – RGY  
SOIC – D  
Tape and reel  
GP1394  
Tube  
GTLP1394  
–40°C to 85°C  
Tape and reel  
Tape and reel  
Tape and reel  
SN74GTLP1394DR  
TSSOP – PW  
TVSOP – DGV  
SN74GTLP1394PWR  
SN74GTLP1394DGVR  
GP394  
GP394  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TI-OPC, OEC, TI are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...25

中文翻译

下载PDF

与SN74GTLP1394RGYR相关器件

型号 品牌 获取价格 描述 数据表
SN74GTLP1395 TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395DGV TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395DGVR TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395DW TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395DWE4 TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395DWR TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395DWRE4 TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395DWRG4 TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
SN74GTLP1395GQNR TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB
SN74GTLP1395PW TI

获取价格

 		TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDB

与SN74GTLP1394RGYR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证