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SN74GTLP1394D PDF预览

SN74GTLP1394D

更新时间： 2024-11-25 22:53:35
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
9页 145K
描述
2-BIT LVTTL-TO-GTL ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY

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SN74GTLP1394D 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SOIC
包装说明：SOIC-16针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.48
Is Samacsys：N控制类型：INDEPENDENT CONTROL
系列：GTLPJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：9.9 mm
逻辑集成电路类型：BUS TRANSCEIVER最大I（ol）：0.024 A
湿度敏感等级：1位数：2
功能数量：1端口数量：3
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：CONFIGURABLE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TUBE峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：20 mA
传播延迟（tpd）：9 ns认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Other Logic ICs
最大供电电压 (Vsup)：3.45 V最小供电电压 (Vsup)：3.15 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：GTLP & LVTTL
宽度：3.91 mmBase Number Matches：1

SN74GTLP1394D 数据手册

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SN74GTLP1394  
2-BIT LVTTL-TO-GTL+ ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER  
WITH SELECTABLE POLARITY  
SCES286 – OCTOBER 1999  
D, DGV, OR PW PACKAGE  
Bidirectional Interface Between GTL+  
(TOP VIEW)  
Signal Levels and LVTTL Logic Levels  
LVTTL Interfaces Are 5-V Tolerant  
High-Drive GTL+ Outputs (100 mA)  
LVTTL Outputs (–24 mA/24 mA)  
OEBY  
Y1  
BIAS V  
GND  
B1  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC  
Y2  
V
GND  
B2  
CC  
Variable Edge-Rate Control (ERC) Input  
Selects GTL+ Rise and Fall Times for  
Optimal Data-Transfer Rate and Signal  
Integrity  
A1  
A2  
GND  
OEAB  
ERC  
V
REF  
T/C  
I
, Power-Up 3-State, and BIAS V  
CC  
off  
Support Live Insertion  
Polarity Control Selects True or  
Complementary Outputs  
Package Options Include Plastic  
Small-Outline (D), Thin Very Small-Outline  
(DGV), and Thin Shrink Small-Outline (PW)  
Packages  
description  
The SN74GTLP1394 is a high-drive 2-bit 3-wire bus transceiver that provides LVTTL-to-GTL+ and  
GTL+-to-LVTTL signal-level translation. It allows for transparent and inverted transparent modes of data  
transfer with separate LVTTL input and LVTTL output pins. The device provides a high-speed interface between  
cards operating at LVTTL logic levels and a backplane operating at GTL+ signal levels and is especially  
designed to work with the Texas Instruments TSB14C01A 1394 Backplane Physical-Layer Controller.  
High-speed (about two times faster than standard LVTTL or TTL) backplane operation is a direct result of  
GTLP’s reduced output swing (<1 V), reduced input threshold levels, improved differential input, and output  
edge control (OEC ). Improved GTLP OEC circuits minimize bus settling time and have been designed and  
tested using several backplane models. The high drive is suitable for driving double-terminated low-impedance  
backplanes using incident-wave switching.  
GTL+ is the Texas Instruments derivative of the Gunning transceiver logic (GTL) JEDEC standard JESD 8-3.  
The AC specification of the SN74GTLP1394 is given only at the preferred higher noise margin GTL+, but the  
user has the flexibility of using this device at either GTL (V = 1.2 V and V  
= 0.8 V) or GTL+ (V = 1.5 V  
TT  
REF  
TT  
and V  
= 1 V) signal levels.  
REF  
Normally, the B port operates at GTL or GTL+ levels. The A inputs, Y outputs, and control inputs are compatible  
with LVTTL logic levels and are 5-V tolerant. V is the reference input voltage for the B port.  
REF  
This device is fully specified for live-insertion applications using I , power-up 3-state, and BIAS V . The I  
off  
off  
CC  
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered  
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power  
down, which prevents driver conflict. The BIAS V  
circuitry precharges and preconditions the B-port  
CC  
input/output connections, preventing disturbance of active data on the backplane during card insertion or  
removal, and permits true live-insertion capability.  
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC  
input voltage between GND and V  
optimize system data-transfer rate and signal integrity to the backplane load.  
adjusts the B-port output rise and fall times. This allows the designer to  
CC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
OEC is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

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SN74GTLP1394D 替代型号

型号 品牌 替代类型 描述 数据表
SN74GTLP1394DR TI

类似代替

 2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK P

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 		2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK P
SN74GTLP1394DRE4 TI

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 		GTLP SERIES, 2-BIT TRANSCEIVER, CONFIGURABLE OUTPUT, PDSO16, GREEN, PLASTIC, MS-012AC, SOI
SN74GTLP1394PW TI

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 		2-BIT LVTTL-TO-GTL ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SELECTABLE POLARITY
SN74GTLP1394PWE4 TI

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SN74GTLP1394PWR TI

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 		2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK P
SN74GTLP1394PWRG4 TI

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