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SN74GTL2107PWR PDF预览

SN74GTL2107PWR

更新时间: 2024-11-26 04:31:15
品牌 Logo 应用领域
德州仪器 - TI 转换器电平转换器驱动程序和接口锁存器接口集成电路光电二极管信息通信管理
页数 文件大小 规格书
10页 124K
描述
12-BIT GTL-/GTL/GTL+ TO LVTTL TRANSLATOR

SN74GTL2107PWR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:TSSOP-28针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:0.91Is Samacsys:N
最大延迟:10 ns输入特性:STANDARD
接口集成电路类型:GTL TO TTL TRANSCEIVERJESD-30 代码:R-PDSO-G28
JESD-609代码:e4长度:9.7 mm
湿度敏感等级:1位数:1
功能数量:13端子数量:28
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出锁存器或寄存器:NONE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP28,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Other Interface ICs最大压摆率:12 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

SN74GTL2107PWR 数据手册

 浏览型号SN74GTL2107PWR的Datasheet PDF文件第2页浏览型号SN74GTL2107PWR的Datasheet PDF文件第3页浏览型号SN74GTL2107PWR的Datasheet PDF文件第4页浏览型号SN74GTL2107PWR的Datasheet PDF文件第5页浏览型号SN74GTL2107PWR的Datasheet PDF文件第6页浏览型号SN74GTL2107PWR的Datasheet PDF文件第7页 
SN74GTL2107  
12-BIT GTL–/GTL/GTL+ TO LVTTL TRANSLATOR  
www.ti.com  
SCLS699JULY 2006  
FEATURES  
PW PACKAGE  
(TOP VIEW)  
Operates as a GTL–/GTL/GTL+ to LVTTL or  
LVTTL to GTL–/GTL/GTL+ Translator  
V
V
CC  
1
2
3
4
5
6
7
8
9
28  
27  
REF  
Series Termination on TTL Output of 30  
1AO  
2AO  
5A  
1BI  
Latch-Up Testing Done to JEDEC Standard  
JESD 78  
26 2BI  
7BO1  
7BO2  
EN2  
25  
24  
23  
22  
ESD Performance Tested Per JESD 22  
6A  
– 2000-V Human-Body Model  
(A114-B, Class II)  
EN1  
11BI  
11A  
9BI  
11BO  
– 200-V Machine Model (A115-A)  
21 5BI  
20 6BI  
19 3BI  
– 1000-V Charged-Device Model (C101)  
3AO 10  
4AO  
10AI1  
10AI2  
4BI  
10BO1  
10BO2  
11  
12  
13  
18  
17  
16  
GND 14  
15 9AO  
DESCRIPTION/ORDERING INFORMATION  
The SN74GTL2107 is a 12-bit translator that interfaces between the 3.3-V LVTTL chip set I/O and the Xeon™  
processor GTL–/GTL/GTL+ I/O. The device is designed for platform health management in dual-processor  
applications.  
PIN DESCRIPTION  
PIN NO.  
SYMBOL  
NAME AND FUNCTION  
GTL reference voltage  
1
VREF  
Data and enable inputs/outputs (LVTTL)  
on all inputs and pin 15 output.  
Remaining outputs are open drain.  
2–6, 8, 10–13,  
15, 23  
ENn  
nAn  
7, 9, 16, 17–22,  
24–27  
nBn  
Data inputs/outputs (GTL–/GTL/GTL+)  
14  
28  
GND  
VCC  
Ground (0 V)  
Positive supply voltage  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
GK2107  
Tube  
SN74GTL2107PW  
SN74GTL2107PWR  
–40°C to 85°C  
TSSOP – PW  
Tape and reel  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Xeon is a trademark of Intel Corporation.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

SN74GTL2107PWR 替代型号

型号 品牌 替代类型 描述 数据表
SN74GTL2107PWRG4 TI

完全替代

12-BIT GTL-/GTL/GTL+ TO LVTTL TRANSLATOR
SN74GTL2107PWG4 TI

完全替代

12-BIT GTL-/GTL/GTL+ TO LVTTL TRANSLATOR
SN74GTL2107PW TI

完全替代

12-BIT GTL-/GTL/GTL+ TO LVTTL TRANSLATOR

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