SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
Member of the Texas Instruments
Widebus Family
I
Supports Partial-Power-Down Mode
off
Operation
EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
Ideal for Use in PC133 Registered DIMM
Applications
DOC (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Dynamic Drive Capability Is Equivalent to
Standard Outputs With I
and I
of
OH
OL
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
±24 mA at 2.5-V V
CC
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical V vs I and V
vs I
curves to illustrate the output impedance and drive capability of the
OL
OL
OH
OH
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )
Circuitry Technology and Applications, literature number SCEA009.
3.2
T
= 25°C
T
= 25°C
A
A
Process = Nominal
Process = Nominal
2.8
2.4
2.0
2.8
2.4
2.0
V
= 3.3 V
CC
1.6
1.2
0.8
0.4
1.6
1.2
0.8
0.4
V
= 2.5 V
CC
V
= 1.8 V
CC
V
= 3.3 V
V
= 2.5 V
CC
CC
V
= 1.8 V
CC
–160 –144 –128 –112 –96 –80 –64 –48 –32 –16
– Output Current – mA
0
17
34
51
68
85 102 119 136 153 170
0
I
– Output Current – mA
I
OH
OL
Figure 1. Output Voltage vs Output Current
This 16-bit universal bus driver is operational at 1.2-V to 3.6-V V , but is designed specifically for 1.65-V to
CC
3.6-V V
operation.
CC
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode
when the latch-enable (LE) input is low. When LE is high, the A data is latched if the clock (CLK) input is held
at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition
of CLK. When OE is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
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