5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74AVC16373DGVR
SN74AVC16373DGVR PDF预览

SN74AVC16373DGVR

更新时间： 2024-09-30 11:07:07
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管逻辑集成电路锁存器总线驱动器总线收发器
页数 文件大小 规格书
11页 169K
描述
具有三态输出的 16 位透明 D 型锁存器 | DGV | 48 | -40 to 85

阅读下载

中文翻译

获取价格

SN74AVC16373DGVR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：TSSOP, TSSOP48,.25,16针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.53控制类型：ENABLE LOW/HIGH
系列：AVCJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：9.7 mm
负载电容（CL）：30 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.012 A湿度敏感等级：1
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.25,16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.04 mAProp。Delay @ Nom-Sup：2.8 ns
传播延迟（tpd）：8.3 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.4 V
标称供电电压 (Vsup)：1.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.4 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：4.4 mmBase Number Matches：1

SN74AVC16373DGVR 数据手册

 浏览型号SN74AVC16373DGVR的Datasheet PDF文件第2页浏览型号SN74AVC16373DGVR的Datasheet PDF文件第3页浏览型号SN74AVC16373DGVR的Datasheet PDF文件第4页浏览型号SN74AVC16373DGVR的Datasheet PDF文件第5页浏览型号SN74AVC16373DGVR的Datasheet PDF文件第6页浏览型号SN74AVC16373DGVR的Datasheet PDF文件第7页 
SN74AVC16373  
16-BIT TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCES156F – DECEMBER 1998 – REVISED FEBRUARY 2000  
Member of the Texas Instruments  
Widebus Family  
I
Supports Partial-Power-Down Mode  
off  
Operation  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
DOC (Dynamic Output Control) Circuit  
Dynamically Changes Output Impedance,  
Resulting in Noise Reduction Without  
Speed Degradation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Package Options Include Plastic Thin  
Shrink Small-Outline (DGG) and Thin Very  
Small-Outline (DGV) Packages  
Dynamic Drive Capability Is Equivalent to  
Standard Outputs With I  
and I  
of  
OH  
OL  
±24 mA at 2.5-V V  
CC  
Overvoltage-Tolerant Inputs/Outputs Allow  
Mixed-Voltage-Mode Data Communications  
description  
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output  
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1  
shows typical V vs I and V  
vs I  
curves to illustrate the output impedance and drive capability of the  
OL  
OL  
OH  
OH  
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is  
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC  
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )  
Circuitry Technology and Applications, literature number SCEA009.  
3.2  
T
= 25°C  
T
= 25°C  
A
A
Process = Nominal  
Process = Nominal  
2.8  
2.4  
2.0  
2.8  
2.4  
2.0  
V
= 3.3 V  
CC  
1.6  
1.2  
0.8  
0.4  
1.6  
1.2  
0.8  
0.4  
V
= 2.5 V  
CC  
V
= 1.8 V  
CC  
V
= 3.3 V  
V
= 2.5 V  
CC  
CC  
V
= 1.8 V  
CC  
–160 –144 –128 –112 –96 –80 –64 –48 –32 –16  
– Output Current – mA  
0
17  
34  
51  
68  
85 102 119 136 153 170  
0
I
– Output Current – mA  
I
OH  
OL  
Figure 1. Output Voltage vs Output Current  
This 16-bit transparent D-type latch is operational at 1.2-V to 3.6-V V , but is designed specifically for 1.65-V  
CC  
to 3.6-V V  
operation.  
CC  
The SN74AVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus  
drivers, and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the  
latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs  
are latched at the levels set up at the D inputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

中文翻译

下载PDF

与SN74AVC16373DGVR相关器件

型号 品牌 获取价格 描述 数据表
SN74AVC16374 TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AVC16374_06 TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AVC16374DGG TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AVC16374DGGE4 TI

获取价格

 		IC AVC SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, PLASTIC, TSSOP-48, Bus Driver/Trans
SN74AVC16374DGGR TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AVC16374DGV TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AVC16374DGVR TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AVC16374GQLR TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AVC16374ZQLR TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AVC16501DGG TI

获取价格

 		AVC SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56

与SN74AVC16373DGVR相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证