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SN74AVC16374DGV

更新时间： 2024-11-15 22:59:15
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
11页 170K
描述
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74AVC16374DGV 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：TSSOP,
针数：48Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.74
系列：AVCJESD-30 代码：R-PDSO-G48
JESD-609代码：e0长度：9.7 mm
逻辑集成电路类型：BUS DRIVER位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
传播延迟（tpd）：8.4 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.4 V标称供电电压 (Vsup)：1.5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mm

SN74AVC16374DGV 数据手册

 浏览型号SN74AVC16374DGV的Datasheet PDF文件第2页浏览型号SN74AVC16374DGV的Datasheet PDF文件第3页浏览型号SN74AVC16374DGV的Datasheet PDF文件第4页浏览型号SN74AVC16374DGV的Datasheet PDF文件第5页浏览型号SN74AVC16374DGV的Datasheet PDF文件第6页浏览型号SN74AVC16374DGV的Datasheet PDF文件第7页 
SN74AVC16374  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000  
Member of the Texas Instruments  
Widebus Family  
I
Supports Partial-Power-Down Mode  
off  
Operation  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
DOC (Dynamic Output Control) Circuit  
Dynamically Changes Output Impedance,  
Resulting in Noise Reduction Without  
Speed Degradation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Package Options Include Plastic Thin  
Shrink Small-Outline (DGG) and Thin Very  
Small-Outline (DGV) Packages  
Dynamic Drive Capability Is Equivalent to  
Standard Outputs With I  
and I  
of  
OH  
OL  
±24 mA at 2.5-V V  
CC  
Overvoltage-Tolerant Inputs/Outputs Allow  
Mixed-Voltage-Mode Data Communications  
description  
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output  
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1  
shows typical V vs I and V  
vs I  
curves to illustrate the output impedance and drive capability of the  
OL  
OL  
OH  
OH  
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is  
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC  
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )  
Circuitry Technology and Applications, literature number SCEA009.  
3.2  
T
= 25°C  
T
= 25°C  
A
A
Process = Nominal  
Process = Nominal  
2.8  
2.4  
2.0  
2.8  
2.4  
2.0  
V
= 3.3 V  
CC  
1.6  
1.2  
0.8  
0.4  
1.6  
1.2  
0.8  
0.4  
V
= 2.5 V  
CC  
V
= 1.8 V  
CC  
V
= 3.3 V  
V
= 2.5 V  
CC  
CC  
V
= 1.8 V  
CC  
–160 –144 –128 –112 –96 –80 –64 –48 –32 –16  
– Output Current – mA  
0
17  
34  
51  
68  
85 102 119 136 153 170  
0
I
– Output Current – mA  
I
OH  
OL  
Figure 1. Output Voltage vs Output Current  
This 16-bit edge-triggered D-type flip-flop is operational at 1.2-V to 3.6-V V , but is designed specifically for  
CC  
1.65-V to 3.6-V V  
operation.  
CC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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