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SN74AVC16834DGGR

更新时间： 2024-09-16 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器输出元件
页数 文件大小 规格书
12页 181K
描述
18-Bit Universal Bus Driver With 3-State Outputs 56-TSSOP -40 to 85

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SN74AVC16834DGGR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：GREEN, PLASTIC, TSSOP-56针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.93Is Samacsys：N
控制类型：ENABLE LOW计数方向：UNIDIRECTIONAL
系列：AVCJESD-30 代码：R-PDSO-G56
JESD-609代码：e4长度：14 mm
负载电容（CL）：30 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.012 A湿度敏感等级：1
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.04 mAProp。Delay @ Nom-Sup：3.1 ns
传播延迟（tpd）：7.8 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.4 V
标称供电电压 (Vsup)：1.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：6.1 mmBase Number Matches：1

SN74AVC16834DGGR 数据手册

 浏览型号SN74AVC16834DGGR的Datasheet PDF文件第2页浏览型号SN74AVC16834DGGR的Datasheet PDF文件第3页浏览型号SN74AVC16834DGGR的Datasheet PDF文件第4页浏览型号SN74AVC16834DGGR的Datasheet PDF文件第5页浏览型号SN74AVC16834DGGR的Datasheet PDF文件第6页浏览型号SN74AVC16834DGGR的Datasheet PDF文件第7页 
SN74AVC16834  
18-BIT UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
SCES183F – DECEMBER 1998 – REVISED FEBRUARY 2000  
Member of the Texas Instruments  
Widebus Family  
I
Supports Partial-Power-Down Mode  
off  
Operation  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Ideal for Use in PC133 Registered DIMM  
Applications  
DOC (Dynamic Output Control) Circuit  
Dynamically Changes Output Impedance,  
Resulting in Noise Reduction Without  
Speed Degradation  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Dynamic Drive Capability Is Equivalent to  
Standard Outputs With I  
and I  
of  
OH  
OL  
Package Options Include Plastic Thin  
Shrink Small-Outline (DGG) and Thin Very  
Small-Outline (DGV) Packages  
±24 mA at 2.5-V V  
CC  
Overvoltage-Tolerant Inputs/Outputs Allow  
Mixed-Voltage-Mode Data Communications  
description  
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output  
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1  
shows typical V vs I and V  
vs I  
curves to illustrate the output impedance and drive capability of the  
OL  
OL  
OH  
OH  
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is  
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC  
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )  
Circuitry Technology and Applications, literature number SCEA009.  
3.2  
T
= 25°C  
T
= 25°C  
A
A
Process = Nominal  
Process = Nominal  
2.8  
2.4  
2.0  
2.8  
2.4  
2.0  
V
= 3.3 V  
CC  
1.6  
1.2  
0.8  
0.4  
1.6  
1.2  
0.8  
0.4  
V
= 2.5 V  
CC  
V
= 1.8 V  
CC  
V
= 3.3 V  
V
= 2.5 V  
CC  
CC  
V
= 1.8 V  
CC  
–160 –144 –128 –112 –96 –80 –64 –48 –32 –16  
– Output Current – mA  
0
17  
34  
51  
68  
85 102 119 136 153 170  
0
I
– Output Current – mA  
I
OH  
OL  
Figure 1. Output Voltage vs Output Current  
This 18-bit universal bus driver is operational at 1.2-V to 3.6-V V , but is designed specifically for 1.65-V to  
CC  
3.6-V V  
operation.  
CC  
Data flow from A to Y is controlled by the output-enable (OE) input. The device operates in the transparent mode  
when the latch-enable (LE) input is low. The A data is latched if the clock (CLK) input is held at a high or low  
logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE  
is high, the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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SN74AVC16834DGGR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AVC16834DGVR TI

完全替代

 具有三态输出的 18 位通用总线驱动器 | DGV | 56 | -40 to 85
74AVC16834DGGRE4 TI

类似代替

 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
PI74AVC16834AE PERICOM

功能相似

 Bus Driver, AVC Series, 1-Func, 18-Bit, True Output, CMOS, PDSO56, 0.240 INCH, GREEN, PLAS

与SN74AVC16834DGGR相关器件

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SN74AVC16834DGV TI

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 		18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SN74AVC16834DGVR TI

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 		具有三态输出的 18 位通用总线驱动器 | DGV | 56 | -40 to 85
SN74AVC16835 TI

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 		18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SN74AVC16835_08 TI

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 		18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SN74AVC16835DGG TI

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 		18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SN74AVC16835DGGR TI

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 		18-Bit Universal Bus Driver With 3-State Outputs 56-TSSOP -40 to 85
SN74AVC16835DGGRE4 TI

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 		IC,BUFFER/DRIVER,SINGLE,18-BIT,AVC/ALVC/VCX-CMOS,TSSOP,56PIN,PLASTIC
SN74AVC16835DGV TI

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 		18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SN74AVC16835DGVR TI

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 		18-Bit Universal Bus Driver With 3-State Outputs 56-TVSOP -40 to 85
SN74AVC16836DGGR TI

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 		AVC SERIES, 20-BIT DRIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56

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