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SN74AVC16722DGGR PDF预览

SN74AVC16722DGGR

更新时间： 2024-11-15 22:59:15
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
12页 201K
描述
22-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

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SN74AVC16722DGGR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：GREEN, PLASTIC, TSSOP-64针数：64
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.31Is Samacsys：N
计数方向：UNIDIRECTIONAL系列：AVC
JESD-30 代码：R-PDSO-G64JESD-609代码：e4
长度：17 mm负载电容（CL）：30 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.012 A
湿度敏感等级：1位数：22
功能数量：1端口数量：2
端子数量：64最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP64,.32,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：0.04 mA
传播延迟（tpd）：6.3 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.2 V
标称供电电压 (Vsup)：1.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：6.1 mm
Base Number Matches：1

SN74AVC16722DGGR 数据手册

 浏览型号SN74AVC16722DGGR的Datasheet PDF文件第2页浏览型号SN74AVC16722DGGR的Datasheet PDF文件第3页浏览型号SN74AVC16722DGGR的Datasheet PDF文件第4页浏览型号SN74AVC16722DGGR的Datasheet PDF文件第5页浏览型号SN74AVC16722DGGR的Datasheet PDF文件第6页浏览型号SN74AVC16722DGGR的Datasheet PDF文件第7页 
SN74AVC16722  
22-BIT FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCES166H – DECEMBER 1998 – REVISED JUNE 2000  
Member of the Texas Instruments  
Widebus Family  
Overvoltage-Tolerant Inputs/Outputs Allow  
Mixed-Voltage-Mode Data Communications  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
I
Supports Partial-Power-Down Mode  
off  
Operation  
DOC (Dynamic Output Control) Circuit  
Dynamically Changes Output Impedance,  
Resulting in Noise Reduction Without  
Speed Degradation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class I  
Packaged in Thin Shrink Small-Outline  
Package  
Dynamic Drive Capability Is Equivalent to  
Standard Outputs With I  
and I  
of  
OH  
OL  
±24 mA at 2.5-V V  
CC  
description  
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output  
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1  
shows typical V vs I and V  
vs I  
curves to illustrate the output impedance and drive capability of the  
OL  
OL  
OH  
OH  
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is  
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports, AVC  
Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC )  
Circuitry Technology and Applications, literature number SCEA009.  
3.2  
T
= 25°C  
T
= 25°C  
A
A
Process = Nominal  
Process = Nominal  
2.8  
2.4  
2.0  
2.8  
2.4  
2.0  
V
= 3.3 V  
CC  
1.6  
1.2  
0.8  
0.4  
1.6  
1.2  
0.8  
0.4  
V
= 2.5 V  
CC  
V
= 1.8 V  
CC  
V
= 3.3 V  
V
= 2.5 V  
CC  
CC  
V
= 1.8 V  
CC  
–160 –144 –128 –112 –96 –80 –64 –48 –32 –16  
– Output Current – mA  
0
17  
34  
51  
68  
85 102 119 136 153 170  
0
I
– Output Current – mA  
I
OH  
OL  
Figure 1. Output Voltage vs Output Current  
This 22-bit flip-flop is operational at 1.2-V to 3.6-V V , but is designed specifically for 1.65-V to 3.6-V V  
CC  
operation.  
CC  
The 22 flip-flops of the SN74AVC16722 are edge-triggered D-type flip-flops with clock-enable (CLKEN) input.  
On the positive transition of the clock (CLK) input, the device stores data into the flip-flops if CLKEN is low. If  
CLKEN is high, no data is stored.  
A buffered output-enable (OE) input places the 22 outputs in either a normal logic state (high or low) or the  
high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.  
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
DOC, EPIC, and Widebus are trademarks of Texas Instruments.  
Copyright 2000, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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SN74AVC16722DGGR 替代型号

型号 品牌 替代类型 描述 数据表
74AVC16722DGGRE4 TI

类似代替

 22-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

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