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SN74AVC16827DGVR PDF预览

SN74AVC16827DGVR

更新时间: 2024-11-16 13:13:47
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
13页 188K
描述
20-Bit Buffer/Driver With 3-State Outputs 56-TVSOP -40 to 85

SN74AVC16827DGVR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:TSSOP, TSSOP56,.25,16针数:56
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.54
其他特性:WITH DUAL OUTPUT ENABLE控制类型:ENABLE LOW
计数方向:UNIDIRECTIONAL系列:AVC
JESD-30 代码:R-PDSO-G56JESD-609代码:e4
长度:11.3 mm负载电容(CL):30 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.012 A
湿度敏感等级:1位数:10
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP56,.25,16
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:3.3 V最大电源电流(ICC):0.04 mA
Prop。Delay @ Nom-Sup:1.7 ns传播延迟(tpd):3.2 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):1.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.4 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:4.4 mm
Base Number Matches:1

SN74AVC16827DGVR 数据手册

 浏览型号SN74AVC16827DGVR的Datasheet PDF文件第2页浏览型号SN74AVC16827DGVR的Datasheet PDF文件第3页浏览型号SN74AVC16827DGVR的Datasheet PDF文件第4页浏览型号SN74AVC16827DGVR的Datasheet PDF文件第5页浏览型号SN74AVC16827DGVR的Datasheet PDF文件第6页浏览型号SN74AVC16827DGVR的Datasheet PDF文件第7页 
SN74AVC16827  
20-BIT BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES176IDECEMBER 1998REVISED JUNE 2005  
FEATURES  
Dynamic Drive Capability Is Equivalent to  
Standard Outputs With IOH and IOL of ±24 mA  
at 2.5-V VCC  
Member of the Texas Instruments Widebus™  
Family  
Overvoltage-Tolerant Inputs/Outputs Allow  
Mixed-Voltage-Mode Data Communications  
EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Ioff Supports Partial-Power-Down Mode  
Operation  
DOC™ (Dynamic Output Control) Circuit  
Dynamically Changes Output Impedance,  
Resulting in Noise Reduction Without Speed  
Degradation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Less Than 2-ns Maximum Propagation Delay  
at 2.5-V and 3.3-V VCC  
Package Options Include Plastic Thin Shrink  
Small-Outline (DGG) and Thin Very  
Small-Outline (DGV) Packages  
DESCRIPTION  
A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output  
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows  
typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At  
the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a  
high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family  
Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC) Circuitry  
Technology and Applications, literature number SCEA009.  
3.2  
T
A
= 25°C  
T
A
= 25°C  
Process = Nominal  
Process = Nominal  
2.8  
2.4  
2.0  
2.8  
2.4  
2.0  
V
CC  
= 3.3 V  
1.6  
1.2  
0.8  
0.4  
1.6  
1.2  
0.8  
0.4  
V
CC  
= 2.5 V  
V
CC  
= 1.8 V  
V
CC  
= 3.3 V  
V
CC  
= 2.5 V  
V
CC  
= 1.8 V  
0
17  
34  
51  
68  
85 102 119 136 153 170  
-160 -144 -128 -112 -96 -80 -64 -48 -32 -16  
- Output Current - mA  
0
I
- Output Current - mA  
I
OH  
OL  
Figure 1. Output Voltage vs Output Current  
This 20-bit noninverting buffer/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to  
3.6-V VCC operation.  
The SN74AVC16827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit  
buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the  
corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section  
are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
The SN74AVC16827 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus, EPIC, DOC are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1998–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
 

SN74AVC16827DGVR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AVC16827DGGR TI

完全替代

具有三态输出的 20 通道、1.2V 至 3.6V 缓冲器 | DGG | 56 | -4
74AVC16827DGGRG4 TI

完全替代

20-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

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IC,BUFFER/DRIVER,SINGLE,18-BIT,AVC/ALVC/VCX-CMOS,TSSOP,56PIN,PLASTIC