SN74AVC16827
20-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES176I–DECEMBER 1998–REVISED JUNE 2005
FEATURES
•
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of ±24 mA
at 2.5-V VCC
•
•
•
Member of the Texas Instruments Widebus™
Family
•
•
•
•
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
Ioff Supports Partial-Power-Down Mode
Operation
DOC™ (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without Speed
Degradation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
Less Than 2-ns Maximum Propagation Delay
at 2.5-V and 3.3-V VCC
Package Options Include Plastic Thin Shrink
Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
DESCRIPTION
A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows
typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At
the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a
high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family
Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry
Technology and Applications, literature number SCEA009.
3.2
T
A
= 25°C
T
A
= 25°C
Process = Nominal
Process = Nominal
2.8
2.4
2.0
2.8
2.4
2.0
V
CC
= 3.3 V
1.6
1.2
0.8
0.4
1.6
1.2
0.8
0.4
V
CC
= 2.5 V
V
CC
= 1.8 V
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
0
17
34
51
68
85 102 119 136 153 170
-160 -144 -128 -112 -96 -80 -64 -48 -32 -16
- Output Current - mA
0
I
- Output Current - mA
I
OH
OL
Figure 1. Output Voltage vs Output Current
This 20-bit noninverting buffer/driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to
3.6-V VCC operation.
The SN74AVC16827 is composed of two 10-bit sections with separate output-enable signals. For either 10-bit
buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the
corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 10-bit buffer section
are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16827 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC, DOC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1998–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.