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SN74AVC126PWR PDF预览

SN74AVC126PWR

更新时间: 2024-09-29 13:13:47
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德州仪器 - TI 输出元件
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SN74AVC126PWR 数据手册

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SN74AVC126  
QUADRUPLE BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES255BAPRIL 1999REVISED DECEMBER 2005  
FEATURES  
EPIC™ (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Overvoltage-Tolerant Inputs/Outputs Allow  
Mixed-Voltage-Mode Data Communications  
DOC™ (Dynamic Output Control) Circuit  
Dynamically Changes Output Impedance,  
Resulting in Noise Reduction Without Speed  
Degradation  
Ioff Supports Partial-Power-Down Mode  
Operation  
Package Options Include Plastic  
Small-Outline (D), Thin Very Small-Outline  
(DGV), and Thin Shrink Small-Outline (PW)  
Packages  
Dynamic Drive Capability Is Equivalent to  
Standard Outputs With IOH and IOL of ±24 mA  
at 2.5-V VCC  
DESCRIPTION  
A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output  
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows  
typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At  
the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a  
high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family  
Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC) Circuitry  
Technology and Applications, literature number SCEA009.  
3.2  
2.8
2.8  
2.4  
2.0  
2.4  
2.0  
1.6  
1.2  
0.8  
1.6  
1.2  
0.8  
0.4  
0.4  
-128 -112 -96 -80 -64  
-32  
-160 -144  
-48  
-16  
0
0
17  
34  
51  
68 85 102 119 136 153 170  
I
- Output Current - mA  
I
OH  
- Output Current - mA  
OL  
Figure 1. Output Voltage vs Output Current  
This quadruple bus buffer gate is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to  
3.6-V VCC operation.  
The SN74AVC126 features independent line drivers with 3-state outputs. Each output is disabled when the  
associated output-enable (OE) input is low.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
The SN74AVC126 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC, DOC are trademarks of Texas Instruments.  
PRODUCT PREVIEW information concerns products in the  
Copyright © 1999–2005, Texas Instruments Incorporated  
formative or design phase of development. Characteristic data and  
other specifications are design goals. Texas Instruments reserves  
the right to change or discontinue these products without notice.  
 

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