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SN74AUP1G97YFPR PDF预览

SN74AUP1G97YFPR

更新时间： 2024-10-31 06:12:55
品牌 Logo 应用领域
德州仪器 - TI 触发器逻辑集成电路栅PC
页数 文件大小 规格书
26页 1100K
描述
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE

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SN74AUP1G97YFPR 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：BGA
包装说明：DSBGA-6针数：6
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.6Samacsys Confidence：
Samacsys Status：ReleasedSamacsys PartID：606890
Samacsys Pin Count：6Samacsys Part Category：Integrated Circuit
Samacsys Package Category：OtherSamacsys Footprint Name：BGA6C40P2X3_117X77X50
Samacsys Released Date：2017-01-12 12:59:53Is Samacsys：N
系列：AUP/ULP/VJESD-30 代码：R-XBGA-B6
JESD-609代码：e1长度：1 mm
负载电容（CL）：30 pF逻辑集成电路类型：LOGIC CIRCUIT
最大I（ol）：0.004 A湿度敏感等级：1
功能数量：1端子数量：6
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：UNSPECIFIED封装代码：BGA
封装等效代码：BGA6,2X3,20封装形状：RECTANGULAR
封装形式：GRID ARRAY包装方法：TR
峰值回流温度（摄氏度）：260电源：1.2/3.3 V
Prop。Delay @ Nom-Sup：26.7 ns认证状态：Not Qualified
施密特触发器：YES座面最大高度：0.5 mm
子类别：Gates最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.4 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：1.4 mmBase Number Matches：1

SN74AUP1G97YFPR 数据手册

 浏览型号SN74AUP1G97YFPR的Datasheet PDF文件第2页浏览型号SN74AUP1G97YFPR的Datasheet PDF文件第3页浏览型号SN74AUP1G97YFPR的Datasheet PDF文件第4页浏览型号SN74AUP1G97YFPR的Datasheet PDF文件第5页浏览型号SN74AUP1G97YFPR的Datasheet PDF文件第6页浏览型号SN74AUP1G97YFPR的Datasheet PDF文件第7页 
SN74AUP1G97  
www.ti.com  
SCES505J –NOVEMBER 2003–REVISED MAY 2010  
LOW-POWER CONFIGURABLE MULTIPLE-FUNCTION GATE  
Check for Samples: SN74AUP1G97  
1
FEATURES  
•
•
•
Available in the Texas Instruments NanoStar™  
Package  
•
•
•
Wide Operating VCC Range of 0.8 V to 3.6 V  
Optimized for 3.3-V Operation  
Low Static-Power Consumption  
(ICC = 0.9 mA Max)  
3.6-V I/O Tolerant to Support Mixed-Mode  
Signal Operation  
Low Dynamic-Power Consumption  
(Cpd = 4.8 pF Typ at 3.3 V)  
•
•
•
tpd = 5.6 ns Max at 3.3 V  
Suitable for Point-to-Point Applications  
•
•
Low Input Capacitance (CI = 1.5 pF Typ)  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Low Noise – Overshoot and Undershoot  
<10% of VCC  
•
ESD Performance Tested Per JESD 22  
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
–
2000-V Human-Body Model  
(A114-B, Class II)  
Includes Schmitt-Trigger Inputs  
–
1000-V Charged-Device Model (C101)  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
C
6
5
4
1
2
3
C
B
GND  
A
6
5
4
B
GND  
A
1
2
3
B
GND  
A
1
2
3
C
6
5
4
VCC  
VCC  
Y
VCC  
Y
Y
DRY PACKAGE  
(TOP VIEW)  
DSF PACKAGE  
(TOP VIEW)  
YFP PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(TOP VIEW)  
A1  
A2  
A1  
A2  
1
2
3
6
5
4
1
6
5
4
1
2
3
6
5
4
1
2
3
6
5
4
B
GND  
A
C
B
GND  
A
C
B
B
GND  
A
C
C
B1 2  
B2  
C2  
B1  
C1  
B2  
C2  
VCC  
Y
VCC  
Y
VCC  
Y
GND  
A
VCC  
Y
C1  
3
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable  
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range  
of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal  
integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2010, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
 
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