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SN74AUC2G80YZPR PDF预览

SN74AUC2G80YZPR

更新时间： 2024-11-16 02:56:51
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
11页 250K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

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中文翻译

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SN74AUC2G80YZPR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：BGA
包装说明：VFBGA, BGA8,2X4,20针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.56系列：AUC
JESD-30 代码：R-XBGA-B8JESD-609代码：e1
长度：1.9 mm负载电容（CL）：15 pF
逻辑集成电路类型：D FLIP-FLOP最大频率@ Nom-Sup：200000000 Hz
最大I（ol）：0.009 A湿度敏感等级：1
位数：1功能数量：2
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：UNSPECIFIED
封装代码：VFBGA封装等效代码：BGA8,2X4,20
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：1.2/2.5 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：3.9 ns传播延迟（tpd）：3.9 ns
认证状态：Not Qualified座面最大高度：0.5 mm
子类别：FF/Latches最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：0.8 V标称供电电压 (Vsup)：1.2 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.5 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：0.9 mm
最小 fmax：275 MHz

SN74AUC2G80YZPR 数据手册

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SCES540A − JANUARY 2004 − REVISED FEBRUARY 2004  
DCT OR DCU PACKAGE  
(TOP VIEW)  
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Optimized for 1.8-V Operation and Is 3.6-V  
I/O Tolerant to Support Mixed-Mode Signal  
Operation  
1
2
3
4
8
7
6
5
1CLK  
1D  
2Q  
GND  
V
CC  
1Q  
2D  
2CLK  
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
D
D
D
D
D
Sub 1-V Operable  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
Max t of 1.9 ns at 1.8 V  
pd  
Low Power Consumption, 10-µA Max I  
CC  
4 5  
3 6  
2 7  
1 8  
GND  
2Q  
1D  
2CLK  
2D  
1Q  
8-mA Output Drive at 1.8 V  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
1CLK  
V
CC  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V V , but is designed specifically  
CC  
for 1.65-V to 1.95-V V  
operation.  
CC  
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on  
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly  
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without  
affecting the levels at the outputs.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
‡
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
Tape and reel  
Tape and reel  
SN74AUC2G80YEPR  
_ _ _UX_  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
SN74AUC2G80YZPR  
−40°C to 85°C  
SSOP − DCT  
Tape and reel  
Tape and reel  
SN74AUC2G80DCTR  
SN74AUC2G80DCUR  
U80_ _ _  
UX_  
VSSOP − DCU  
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available  
at www.ti.com/sc/package.  
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and  
one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition  
(1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

中文翻译

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SN74AUC2G80YZPR 替代型号

型号 品牌 替代类型 描述 数据表
SN74AUC1G74DCUR TI

类似代替

 SINGLE POSITIVE EDGE TRIGGERED D TYPE FLIP FLOP WITH CLEAR AND PRESET
SN74AUC1G74DCTR TI

类似代替

 SINGLE POSITIVE EDGE TRIGGERED D TYPE FLIP FLOP WITH CLEAR AND PRESET
SN74AUP1G74DCUR TI

功能相似

 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET

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