Datasheet > 逻辑 > 总线驱动器/收发器> SN74AUC32245

SN74AUC32245

更新时间： 2024-11-16 04:35:31

品牌	Logo	应用领域
德州仪器 - TI		总线收发器输出元件
页数	文件大小	规格书
12页	390K
描述
32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SN74AUC32245 数据手册

SN74AUC32245

32-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

www.ti.com

SCES410C–AUGUST 2002–REVISED MARCH 2005

FEATURES

•

Max t_pdof 2 ns at 1.8 V

•

Member of the Texas Instruments Widebus+™

Family

Low Power Consumption, 40-µA Max I_CC

±8-mA Output Drive at 1.8 V

•

Optimized for 1.8-V Operation and Is 3.6-V I/O

Tolerant to Support Mixed-Mode Signal

Operation

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

•

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

•

I_offSupports Partial-Power-Down Mode

Operation

Sub-1-V Operable

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This 32-bit noninverting bus transceiver is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for

1.65-V to 1.95-V V_CCoperation.

The SN74AUC32245 is designed for asynchronous communication between data buses. The control-function

implementation minimizes external timing requirements.

This device can be used as four 8-bit transceivers, two 16-bit transceivers, or one 32-bit transceiver. It allows

data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the

direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses

are effectively isolated.

To ensure the high-impedance state during power up or power down, OE should be tied to V_CCthrough a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

–40°C to 85°C

LFBGA – GKE

Tape and reel

SN74AUC32245GKER

MM245

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus+ is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...12

中文翻译

下载PDF

与SN74AUC32245相关器件

型号	品牌	获取价格	描述	数据表
SN74AUC32245GKER	TI	获取价格	32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74AUC32245ZKER	TI	获取价格	32-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SN74AUC32374	TI	获取价格	32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AUC32374GKER	TI	获取价格	AUC SERIES, QUAD 8-BIT DRIVER, TRUE OUTPUT, PBGA96, PLASTIC, LFBGA-96
SN74AUC32374ZKER	TI	获取价格	32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74AUC32RGYR	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-OR GATE
SN74AUC32RGYRG4	TI	获取价格	QUADRUPLE 2-INPUT POSITIVE-OR GATE
SN74AUC34	TI	获取价格	HEX BUFFER GATE
SN74AUC34RGYR	TI	获取价格	HEX BUFFER GATE
SN74AUC34RGYRG4	TI	获取价格	HEX BUFFER GATE

与SN74AUC32245相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

13
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

7
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

36
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

31

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74AUC32245

SN74AUC32245 数据手册

与SN74AUC32245相关器件

与SN74AUC32245相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SN74AUC32245

SN74AUC32245 数据手册

与SN74AUC32245相关器件

与SN74AUC32245相关文章

您还可以找

您在本页遇到什么问题？