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SN74AUC2G86

更新时间： 2024-11-15 22:11:51

品牌	Logo	应用领域
德州仪器 - TI		输入元件
页数	文件大小	规格书
10页	233K
描述
DUAL 2-INPUT EXCLUSIVE-OR GATE

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SN74AUC2G86 数据手册

SN74AUC2G86

DUAL 2-INPUT EXCLUSIVE-OR GATE

SCES479 – AUGUST 2003

DCT OR DCU PACKAGE

(TOP VIEW)

Available in the Texas Instruments

NanoStar and NanoFree Packages

Optimized for 1.8-V Operation and Is 3.6-V

I/O Tolerant to Support Mixed-Mode Signal

Operation

Supports Partial-Power-Down Mode

off

GND

Operation

Sub 1-V Operable

YEP OR YZP PACKAGE

(BOTTOM VIEW)

Max t of 1.7 ns at 1.8 V

Low Power Consumption, 10-µA Max I

8-mA Output Drive at 1.8 V

4 5

3 6

2 7

1 8

GND

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

description/ordering information

This dual 2-input exclusive-OR gate is operational at 0.8-V to 2.7-V V , but is designed specifically for 1.65-V

to 1.95-V V

operation.

The SN74AUC2G86 performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.

A common application is as a true/complement element. If the input is low, the other input is reproduced in true

form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

‡

NanoStar – WCSP (DSBGA)

0.23-mm Large Bump – YEP

SN74AUC2G86YEPR

SN74AUC2G86YZPR

Tape and reel

_ _ _UH_

NanoFree – WCSP (DSBGA)

0.23-mm Large Bump – YZP (Pb-free)

–40°C to 85°C

SSOP – DCT

Tape and reel

SN74AUC2G86DCTR

SN74AUC2G86DCUR

U86_ _ _

U86_

VSSOP – DCU

†

‡

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available

at www.ti.com/sc/package.

DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

DCU: The actual top-side marking has one additional character that designates the assembly/test site.

YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and

one following character to designate the assembly/test site.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar and NanoFree are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...10

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与SN74AUC2G86相关器件

型号	品牌	获取价格	描述	数据表
SN74AUC2G86_09	TI	获取价格	DUAL 2-INPUT EXCLUSIVE-OR GATE
SN74AUC2G86DCTR	TI	获取价格	DUAL 2-INPUT EXCLUSIVE-OR GATE
SN74AUC2G86DCTRE4	TI	获取价格	DUAL 2-INPUT EXCLUSIVE-OR GATE
SN74AUC2G86DCTRG4	TI	获取价格	DUAL 2-INPUT EXCLUSIVE-OR GATE
SN74AUC2G86DCUR	TI	获取价格	DUAL 2-INPUT EXCLUSIVE-OR GATE
SN74AUC2G86DCURE4	TI	获取价格	DUAL 2-INPUT EXCLUSIVE-OR GATE
SN74AUC2G86DCURG4	TI	获取价格	DUAL 2-INPUT EXCLUSIVE-OR GATE
SN74AUC2G86YEPR	TI	获取价格	DUAL 2-INPUT EXCLUSIVE-OR GATE
SN74AUC2G86YZPR	TI	获取价格	DUAL 2-INPUT EXCLUSIVE-OR GATE
SN74AUC2GU04	TI	获取价格	DUAL INVERTER GATE

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