5秒后页面跳转
SN74AUC2G02_09 PDF预览

SN74AUC2G02_09

更新时间: 2024-11-02 06:12:55
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
13页 536K
描述
DUAL 2-INPUT POSITIVE-NOR GATE

SN74AUC2G02_09 数据手册

 浏览型号SN74AUC2G02_09的Datasheet PDF文件第2页浏览型号SN74AUC2G02_09的Datasheet PDF文件第3页浏览型号SN74AUC2G02_09的Datasheet PDF文件第4页浏览型号SN74AUC2G02_09的Datasheet PDF文件第5页浏览型号SN74AUC2G02_09的Datasheet PDF文件第6页浏览型号SN74AUC2G02_09的Datasheet PDF文件第7页 
SN74AUC2G02  
DUAL 2-INPUT POSITIVE-NOR GATE  
www.ti.com  
SCES441CMAY 2003REVISED JANUARY 2007  
FEATURES  
Available in the Texas Instruments  
NanoFree™ Package  
Low Power Consumption, 10 µA at 1.8 V  
±8-mA Output Drive at 1.8 V  
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
Ioff Supports Partial Power-Down-Mode  
Operation  
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Sub-1-V Operable  
1000-V Charged-Device Model (C101)  
Max tpd of 1.8 ns at 1.8 V  
DESCRIPTION/ORDERING INFORMATION  
This dual 2-input positive-NOR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V  
to 1.95-V VCC operation.  
The SN74AUC2G02 performs the Boolean function Y = A + B or Y = A B in positive logic.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
Reel of 3000  
SN74AUC2G02YZPR  
_ _ _UB_  
–40°C to 85°C  
SSOP – DCT  
Reel of 3000  
Reel of 3000  
SN74AUC2G02DCTR  
SN74AUC2G02DCUR  
U02_  
U02_  
VSSOP – DCU  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

与SN74AUC2G02_09相关器件

型号 品牌 获取价格 描述 数据表
SN74AUC2G02DCTR TI

获取价格

DUAL 2-INPUT POSITIVE-NOR GATE
SN74AUC2G02DCTRE4 TI

获取价格

DUAL 2-INPUT POSITIVE-NOR GATE
SN74AUC2G02DCTRG4 TI

获取价格

DUAL 2-INPUT POSITIVE-NOR GATE
SN74AUC2G02DCUR TI

获取价格

DUAL 2-INPUT POSITIVE-NOR GATE
SN74AUC2G02DCURE4 TI

获取价格

DUAL 2-INPUT POSITIVE-NOR GATE
SN74AUC2G02DCURG4 TI

获取价格

DUAL 2-INPUT POSITIVE-NOR GATE
SN74AUC2G02YEPR TI

获取价格

DUAL 2-INPUT POSITIVE-NOR GATE
SN74AUC2G02YZPR TI

获取价格

DUAL 2-INPUT POSITIVE-NOR GATE
SN74AUC2G04 TI

获取价格

DUAL INVERTER GATE
SN74AUC2G04_1 TI

获取价格

DUAL INVERTER GATE