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SN74AUC2G02DCTRE4

更新时间： 2024-11-24 06:12:55
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
13页 536K
描述
DUAL 2-INPUT POSITIVE-NOR GATE

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SN74AUC2G02DCTRE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：GREEN, PLASTIC, SSOP-8针数：8
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.64Is Samacsys：N
系列：AUCJESD-30 代码：R-PDSO-G8
JESD-609代码：e4长度：2.95 mm
负载电容（CL）：15 pF逻辑集成电路类型：NOR GATE
最大I（ol）：0.005 A湿度敏感等级：1
功能数量：2输入次数：2
端子数量：8最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LSSOP
封装等效代码：SSOP8,.16封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：1.2/2.5 V
Prop。Delay @ Nom-Sup：3.5 ns传播延迟（tpd）：3.5 ns
认证状态：Not Qualified施密特触发器：NO
座面最大高度：1.3 mm子类别：Gates
最大供电电压 (Vsup)：2.7 V最小供电电压 (Vsup)：0.8 V
标称供电电压 (Vsup)：1.2 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：2.8 mm
Base Number Matches：1

SN74AUC2G02DCTRE4 数据手册

 浏览型号SN74AUC2G02DCTRE4的Datasheet PDF文件第2页浏览型号SN74AUC2G02DCTRE4的Datasheet PDF文件第3页浏览型号SN74AUC2G02DCTRE4的Datasheet PDF文件第4页浏览型号SN74AUC2G02DCTRE4的Datasheet PDF文件第5页浏览型号SN74AUC2G02DCTRE4的Datasheet PDF文件第6页浏览型号SN74AUC2G02DCTRE4的Datasheet PDF文件第7页 
SN74AUC2G02  
DUAL 2-INPUT POSITIVE-NOR GATE  
www.ti.com  
SCES441C–MAY 2003–REVISED JANUARY 2007  
FEATURES  
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
•
Low Power Consumption, 10 µA at 1.8 V  
±8-mA Output Drive at 1.8 V  
•
Optimized for 1.8-V Operation and Is 3.6-V I/O  
Tolerant to Support Mixed-Mode Signal  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
ESD Protection Exceeds JESD 22  
•
Ioff Supports Partial Power-Down-Mode  
Operation  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
•
•
Sub-1-V Operable  
1000-V Charged-Device Model (C101)  
Max tpd of 1.8 ns at 1.8 V  
DESCRIPTION/ORDERING INFORMATION  
This dual 2-input positive-NOR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V  
to 1.95-V VCC operation.  
The SN74AUC2G02 performs the Boolean function Y = A + B or Y = A • B in positive logic.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
Reel of 3000  
SN74AUC2G02YZPR  
_ _ _UB_  
–40°C to 85°C  
SSOP – DCT  
Reel of 3000  
Reel of 3000  
SN74AUC2G02DCTR  
SN74AUC2G02DCUR  
U02_  
U02_  
VSSOP – DCU  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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