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SN74ALVCH16834DGV

更新时间： 2024-11-04 20:00:19
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路电视
页数 文件大小 规格书
10页 133K
描述
ALVC/VCX/A SERIES, 18-BIT DRIVER, TRUE OUTPUT, PDSO56, PLASTIC, TVSOP-56

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SN74ALVCH16834DGV 技术参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：TSSOP,针数：56
Reach Compliance Code：unknown风险等级：5.84
系列：ALVC/VCX/AJESD-30 代码：R-PDSO-G56
长度：11.3 mm逻辑集成电路类型：BUS DRIVER
位数：18功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.4 mm
端子位置：DUAL宽度：4.4 mm
Base Number Matches：1

SN74ALVCH16834DGV 数据手册

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SN74ALVCH16834  
18-BIT UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
SCES190 – FEBRUARY 1999  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
NC  
NC  
Y1  
GND  
Y2  
Y3  
GND  
NC  
A1  
GND  
A2  
A3  
2
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
3
4
5
Package Options Include Plastic Shrink  
Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages  
6
7
V
V
CC  
Y4  
CC  
8
A4  
A5  
A6  
GND  
A7  
9
Y5  
Y6  
GND  
Y7  
Y8  
Y9  
Y10  
Y11  
Y12  
GND  
Y13  
Y14  
Y15  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
description  
This 18-bit universal bus driver is designed for  
1.65-V to 3.6-V V operation.  
A8  
A9  
CC  
Data flow from A to Y is controlled by the  
output-enable (OE) input. The device operates in  
the transparent mode when the latch-enable (LE)  
inputislow. TheAdataislatchediftheclock(CLK)  
input is held at a high or low logic level. If LE is  
high, the A data is stored in the latch/flip-flop on  
the low-to-high transition of CLK. When OE is  
high, the outputs are in the high-impedance state.  
A10  
A11  
A12  
GND  
A13  
A14  
A15  
V
V
CC  
CC  
Y16  
Y17  
GND  
Y18  
OE  
A16  
A17  
GND  
A18  
CLK  
GND  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
CC  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
LE  
Active bus-hold circuitry is provided to hold  
unused or floating data inputs at a valid logic level.  
NC – No internal connection  
The SN74ALVCH16834 is characterized for  
operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

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SN74ALVCH16835 TI

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SN74ALVCH16835_08 TI

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SN74ALVCH16835DGG TI

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SN74ALVCH16835DGGR TI

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SN74ALVCH16835DGV TI

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 		18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
SN74ALVCH16835DGVR TI

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SN74ALVCH16835DL TI

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 		18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

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