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SN74ALVCH16863DGGR PDF预览

SN74ALVCH16863DGGR

更新时间： 2024-09-17 02:58:39
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德州仪器 - TI 光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
8页 118K
描述
18-BIT TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74ALVCH16863DGGR 数据手册

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SN74ALVCH16863  
18-BIT TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1OEAB  
1B1  
1B2  
GND  
1B3  
1OEBA  
1A1  
1A2  
GND  
1A3  
1A4  
2
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
4
5
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
6
1B4  
7
V
V
CC  
CC  
8
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
1B5  
1B6  
1B7  
GND  
1B8  
1B9  
GND  
GND  
2B1  
2B2  
GND  
2B3  
2B4  
2B5  
1A5  
1A6  
1A7  
GND  
1A8  
1A9  
GND  
GND  
2A1  
2A2  
GND  
2A3  
2A4  
2A5  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
This 18-bit bus transceiver is designed for 1.65-V  
to 3.6-V V operation.  
CC  
The SN74ALVCH16863 is an 18-bit noninverting  
transceiver designed for synchronous  
communication between data buses. The  
control-function implementation minimizes  
external timing requirements.  
V
V
CC  
CC  
2B6  
2B7  
GND  
2B8  
2B9  
2OEAB  
2A6  
2A7  
GND  
2A8  
2A9  
The SN74ALVCH16863 can be used as two 9-bit  
transceivers or one 18-bit transceiver. They allow  
data transmission from the A bus to the B bus or  
fromtheBbustotheAbus, dependingonthelogic  
level at the output-enable (OEAB or OEBA)  
inputs.  
2OEBA  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16863 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each 9-bit section)  
INPUTS  
OPERATION  
OEAB  
OEBA  
H
L
L
H
H
B data to A bus  
A data to B bus  
Isolation  
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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