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SN74ALVCH16841

更新时间: 2024-11-19 23:09:43
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德州仪器 - TI 锁存器输出元件
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10页 135K
描述
20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

SN74ALVCH16841 数据手册

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SN74ALVCH16841  
20-BIT BUS-INTERFACE D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCES043D – JULY 1995 – REVISED FEBRUARY 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
56  
55  
54  
53  
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32  
31  
30  
29  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
2
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
4
5
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
6
7
V
V
CC  
CC  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
8
1Q5  
1Q6  
1Q7  
GND  
1Q8  
1Q9  
1Q10  
2Q1  
2Q2  
2Q3  
GND  
2Q4  
2Q5  
2Q6  
1D5  
1D6  
1D7  
GND  
1D8  
1D9  
1D10  
2D1  
2D2  
2D3  
GND  
2D4  
2D5  
2D6  
9
10  
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28  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
This 20-bit bus-interface D-type latch is designed  
for 1.65-V to 3.6-V V operation.  
CC  
The SN74ALVCH16841 features 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. This device is  
particularly suitable for implementing buffer  
registers, unidirectional bus drivers, and working  
registers.  
V
V
CC  
CC  
2Q7  
2Q8  
GND  
2Q9  
2Q10  
2OE  
2D7  
2D8  
GND  
2D9  
2D10  
2LE  
TheSN74ALVCH16841 can be used as two 10-bit  
latches or one 20-bit latch. The 20 latches are  
transparent D-type latches. The device has  
noninverting data (D) inputs and provides true  
data at its outputs. While the latch-enable (1LE or  
2LE) input is high, the Q outputs of the  
corresponding 10-bit latch follow the D inputs.  
When LE is taken low, the Q outputs are latched  
at the levels set up at the D inputs.  
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch  
in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state,  
the outputs neither load nor drive the bus lines significantly.  
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16841 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus and EPIC are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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