5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> SN74ALVCH16836DL
SN74ALVCH16836DL PDF预览

SN74ALVCH16836DL

更新时间： 2024-11-19 22:36:15
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
10页 136K
描述
20-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN74ALVCH16836DL 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SSOP包装说明：SSOP, SSOP56,.4
针数：56Reach Compliance Code：unknown
风险等级：5.84Is Samacsys：N
控制类型：ENABLE LOW系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56长度：18.415 mm
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
位数：20功能数量：1
端口数量：2端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP56,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
座面最大高度：2.79 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mmBase Number Matches：1

SN74ALVCH16836DL 数据手册

 浏览型号SN74ALVCH16836DL的Datasheet PDF文件第2页浏览型号SN74ALVCH16836DL的Datasheet PDF文件第3页浏览型号SN74ALVCH16836DL的Datasheet PDF文件第4页浏览型号SN74ALVCH16836DL的Datasheet PDF文件第5页浏览型号SN74ALVCH16836DL的Datasheet PDF文件第6页浏览型号SN74ALVCH16836DL的Datasheet PDF文件第7页 
SN74ALVCH16836  
20-BIT UNIVERSAL BUS DRIVER  
WITH 3-STATE OUTPUTS  
SCES089C – OCTOBER 1996 – REVISED FEBRUARY 1999  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
OE  
Y1  
Y2  
GND  
Y3  
Y4  
1
2
3
4
5
6
7
8
9
10  
56 CLK  
55 A1  
54 A2  
53 GND  
52 A3  
51 A4  
Designed to Comply With JEDEC 168-Pin  
and 200-Pin SDRAM Buffered DIMM  
Specification  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
V
50  
V
CC  
Y5  
CC  
49 A5  
48 A6  
Package Options Include Plastic Shrink  
Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
Y6  
Y7  
GND 11  
Y8 12  
47  
A7  
46 GND  
45 A8  
description  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
Y9  
Y10  
Y11  
Y12  
Y13  
GND  
Y14  
Y15  
Y16  
A9  
A10  
A11  
A12  
A13  
GND  
A14  
A15  
A16  
This 20-bit universal bus driver is designed for  
1.65-V to 3.6-V V operation.  
CC  
Data flow from A to Y is controlled by the  
output-enable (OE) input. The device operates in  
the transparent mode when the latch-enable (LE)  
inputislow. TheAdataislatchediftheclock(CLK)  
input is held at a high or low logic level. If LE is  
high, the A data is stored in the latch/flip-flop on  
the low-to-high transition of CLK. When OE is  
high, the outputs are in the high-impedance state.  
V
V
CC  
CC  
Y17  
Y18  
GND  
Y19  
Y20  
NC  
A17  
A18  
GND  
A19  
A20  
LE  
To ensure the high-impedance state during power  
up or power down, OE should be tied to V  
through a pullup resistor; the minimum value of  
the resistor is determined by the current-sinking  
capability of the driver.  
CC  
NC – No internal connection  
Active bus-hold circuitry is provided to hold  
unused or floating data inputs at a valid logic level.  
The SN74ALVCH16836 is characterized for  
operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCT PREVIEW information concerns products in the formative or  
design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right to  
change or discontinue these products without notice.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

中文翻译

下载PDF

与SN74ALVCH16836DL相关器件

型号 品牌 获取价格 描述 数据表
SN74ALVCH16841 TI

获取价格

 		20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALVCH16841DGG TI

获取价格

 		20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALVCH16841DGGR TI

获取价格

 		20-Bit Bus-Interface D-Type Latch With 3-State Outputs 56-TSSOP -40 to 85
SN74ALVCH16841DL TI

获取价格

 		20-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74ALVCH16841DLR TI

获取价格

 		具有三态输出的 9 位总线接口 D 类锁存器 | DL | 56 | -40 to 85
SN74ALVCH16843DGGR TI

获取价格

 		ALVC/VCX/A SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-56
SN74ALVCH16843DLR TI

获取价格

 		ALVC/VCX/A SERIES, DUAL 9-BIT DRIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLASTIC, SSOP-56
SN74ALVCH16863 TI

获取价格

 		18-BIT TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16863_09 TI

获取价格

 		18-BIT TRANSCEIVER WITH 3-STATE OUTPUTS
SN74ALVCH16863DGG TI

获取价格

 		18-BIT TRANSCEIVER WITH 3-STATE OUTPUTS

与SN74ALVCH16836DL相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证