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SN74ALVCH16646DGGR

更新时间： 2024-11-06 13:13:47
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德州仪器 - TI 总线收发器输出元件
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SN74ALVCH16646DGGR 数据手册

 浏览型号SN74ALVCH16646DGGR的Datasheet PDF文件第2页浏览型号SN74ALVCH16646DGGR的Datasheet PDF文件第3页浏览型号SN74ALVCH16646DGGR的Datasheet PDF文件第4页浏览型号SN74ALVCH16646DGGR的Datasheet PDF文件第5页浏览型号SN74ALVCH16646DGGR的Datasheet PDF文件第6页浏览型号SN74ALVCH16646DGGR的Datasheet PDF文件第7页 
SN74ALVCH16646  
16-BIT BUS TRANSCEIVER AND REGISTER  
WITH 3-STATE OUTPUTS  
SCES032E– JULY 1995 – REVISED FEBRUARY 1999  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
1DIR  
1CLKAB  
1SAB  
GND  
1OE  
2
1CLKBA  
1SBA  
GND  
1B1  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
3
4
5
1A1  
1A2  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
6
1B2  
7
V
V
CC  
CC  
8
1A3  
1A4  
1A5  
GND  
1A6  
1A7  
1A8  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B3  
1B4  
1B5  
GND  
1B6  
1B7  
1B8  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL), Thin Shrink  
Small-Outline (DGG), and Thin Very  
Small-Outline (DGV) Packages  
description  
This 16-bit bus transceiver and register is  
designed for 1.65-V to 3.6-V V operation.  
CC  
The SN74ALVCH16646 can be used as two 8-bit  
transceivers or one 16-bit transceiver. Data on the  
A or B bus is clocked into the registers on the  
low-to-high transition of the appropriate clock  
(CLKAB or CLKBA) input. Figure 1 illustrates the  
four fundamental bus-management functions that  
can be performed with the SN74ALVCH16646.  
V
V
CC  
CC  
2A7  
2A8  
GND  
2B7  
2B8  
GND  
2SBA  
2CLKBA  
2OE  
2SAB  
2CLKAB  
2DIR  
Output-enable (OE) and direction-control (DIR)  
inputs are provided to control the transceiver  
functions. Inthetransceivermode, datapresentat  
the high-impedance port may be stored in either  
register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent  
mode)data. Thecircuitryusedforselectcontroleliminatesthetypicaldecodingglitchthatoccursinamultiplexer  
during the transition between stored and real-time data. DIR determines which bus receives data when OE is  
low. In the isolation mode (OE high), A data may be stored in one register and/or B data may be stored in the  
other register.  
When an output function is disabled, the input function is still enabled and may be used to store and transmit  
data. Only one of the two buses, A or B, can be driven at a time.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74ALVCH16646 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

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SN74ALVCH16646DGGR 替代型号

型号 品牌 替代类型 描述 数据表
74ALVCH16646DGGRG4 TI

完全替代

 具有三态输出的 16 位总线收发器和寄存器 | DGG | 56 | -40 to 85
74ALVCH16646DGGRE4 TI

完全替代

 16-Bit Bus Transceiver And Register With 3-State Outputs 56-TSSOP -40 to 85

与SN74ALVCH16646DGGR相关器件

型号 品牌 获取价格 描述 数据表
SN74ALVCH16646DGV TI

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 		16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SN74ALVCH16646DGVR TI

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 		具有三态输出的 16 位总线收发器和寄存器 | DGV | 56 | -40 to 85
SN74ALVCH16646DL TI

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 		16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS
SN74ALVCH16646DLR TI

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 		16-Bit Bus Transceiver And Register With 3-State Outputs 56-SSOP -40 to 85
SN74ALVCH16652DGGR TI

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 		ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, PLASTIC, TSSOP-
SN74ALVCH16652DL TI

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 		ALVC/VCX/A SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, PLA
SN74ALVCH16721 TI

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 		3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
SN74ALVCH16721DGG TI

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 		3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS
SN74ALVCH16721DGGR TI

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 		具有三态输出的 3.3V 20 位触发器 | DGG | 56 | -40 to 85
SN74ALVCH16721DGV TI

获取价格

 		3.3-V 20-BIT FLIP-FLOP WITH 3-STATE OUTPUTS

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