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SN74ALVCH162841DLR PDF预览

SN74ALVCH162841DLR

更新时间: 2024-11-18 20:51:51
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
9页 276K
描述
ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56, 0.300 INCH, GREEN, PLASTIC, SSOP-56

SN74ALVCH162841DLR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP56,.4针数:56
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.46系列:ALVC/VCX/A
JESD-30 代码:R-PDSO-G56长度:18.415 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.012 A位数:10
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP56,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:4.3 ns
传播延迟(tpd):5.9 ns认证状态:Not Qualified
座面最大高度:2.79 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.49 mmBase Number Matches:1

SN74ALVCH162841DLR 数据手册

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ꢀ ꢁ ꢂꢃꢄꢅꢆ ꢇꢈ ꢉꢊ ꢋꢌ ꢍꢂ  
ꢈ ꢎꢏꢐ ꢑ ꢑ ꢒ ꢊ ꢎꢏꢐ ꢑ ꢂꢓꢓ ꢔꢕꢇꢇ ꢓ ꢔꢐ ꢄ ꢕꢔ  
ꢖ ꢐꢑ ꢆ ꢌ ꢎꢇꢑꢂꢑ ꢕ ꢒ ꢗꢑ ꢘ ꢗꢑꢇ  
SCES624 − FEBRUARY 2005  
DBB PACKAGE  
(TOP VIEW)  
D
D
Member of the Texas Instruments  
WidebusFamily  
Output Ports Have Series Damping  
Resistors, So No External Resistors Are  
Required  
2Y2  
1Y2  
GND  
2Y1  
1Y3  
2Y3  
GND  
1Y4  
2Y4  
1
80  
79  
78  
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43  
42  
41  
2
3
D
D
Diodes on Inputs Clamp Overshoot  
4
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
1Y1  
5
V
V
6
CC  
CC  
A1  
A2  
GND  
A3  
A4  
GND  
A5  
A6  
1Y5  
2Y5  
GND  
1Y6  
2Y6  
GND  
1Y7  
2Y7  
7
8
D
D
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
9
10  
11  
12  
13  
14  
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17  
18  
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39  
40  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
description/ordering information  
V
V
CC  
CC  
This 1-bit to 2-bit address driver is designed for  
A7  
A8  
GND  
A9  
OE1  
OE2  
A10  
GND  
A11  
A12  
1Y8  
2Y8  
GND  
1Y9  
2Y9  
1Y10  
2Y10  
GND  
1Y11  
2Y11  
2.3-V to 3.6-V V  
operation.  
CC  
Diodes to V  
clamp overshoot.  
have been added on the inputs to  
CC  
Active bus-hold circuitry holds unused or undriven  
inputs at a valid logic state. Use of pullup or  
pulldown resistors with the bus-hold circuitry is not  
recommended.  
The outputs, which are designed to sink up to  
12 mA, include series damping resistors to reduce  
overshoot and undershoot.  
V
V
CC  
CC  
A13  
A14  
GND  
A15  
A16  
GND  
A17  
A18  
1Y12  
2Y12  
GND  
1Y13  
2Y13  
GND  
1Y14  
2Y14  
The ALVCHS162830A is an improved version of  
the LVCHS162830 (non-A version) and has been  
optimized for lower power consumption and  
higher AC drive. Higher AC drive provides  
capability to drive loads with a faster edge rate.  
To ensure the high-impedance state during power  
up or power down, the output-enable (OE) input  
V
V
CC  
CC  
should be tied to V  
through a pullup resistor; the  
2Y18  
1Y18  
GND  
2Y17  
1Y17  
1Y15  
2Y15  
GND  
1Y16  
2Y16  
CC  
minimum value of the resistor is determined by the  
current-sinking capability of the driver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
ꢑꢥ  
Copyright 2005, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74ALVCH162841DLR 替代型号

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SN74ALVCH16841DLR TI

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