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SN74ALVCH16373_07

更新时间： 2024-11-18 05:29:35
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德州仪器 - TI 锁存器输出元件
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19页 489K
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16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74ALVCH16373_07 数据手册

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SN74ALVCH16373  
16-BIT TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES020I–JULY 1995–REVISED NOVEMBER 2005  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
1
48  
47  
46  
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42  
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40  
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38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Max tpd of 3.6 ns at 3.3 V  
2
3
±24-mA Output Drive at 3.3 V  
4
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
5
6
•
•
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
7
V
CC  
V
CC  
8
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
9
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
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22  
23  
24  
XXXX  
DESCRIPTION/ORDERING INFORMATION  
This 16-bit transparent D-type latch is designed for  
1.65-V to 3.6-V VCC operation.  
V
CC  
V
CC  
The SN74ALVCH16373 is particularly suitable for  
implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers. This device can  
be used as two 8-bit latches or one 16-bit latch.  
When the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is taken  
low, the Q outputs are latched at the levels set up at  
the D inputs.  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2LE  
A buffered output-enable (OE) input can be used to  
place the eight outputs in either a normal logic state  
(high or low logic levels) or the high-impedance state.  
In the high-impedance state, the outputs neither  
load nor drive the buslines significantly. The  
high-impedance state and the increased drive provide  
the capability to drive bus lines without need for  
interface or pullup components. OE does not affect  
internal operations of the latch. Old data can be  
retained or new data can be entered while the  
outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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